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{"id":"https://openalex.org/W1981630413","doi":"https://doi.org/10.1109/etsym.2010.5512749","title":"Design and implementation of Automatic Test Equipment IP module","display_name":"Design and implementation of Automatic Test Equipment IP module","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W1981630413","doi":"https://doi.org/10.1109/etsym.2010.5512749","mag":"1981630413"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/etsym.2010.5512749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041035552","display_name":"S. Fransi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210121017","display_name":"Gesellschaft f\u00fcr Fertigungstechnik und Entwicklung","ror":"https://ror.org/02hbmds06","country_code":"DE","type":"other","lineage":["https://openalex.org/I4210121017"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"S. Fransi","raw_affiliation_strings":["SFPe engineering, Munich, Germany"],"affiliations":[{"raw_affiliation_string":"SFPe engineering, Munich, Germany","institution_ids":["https://openalex.org/I4210121017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022206889","display_name":"Gerard Farr\u00e9","orcid":"https://orcid.org/0000-0001-8770-5430"},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"G. L. Farre","raw_affiliation_strings":["[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069617045","display_name":"L. G. Deiros","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"L. G. Deiros","raw_affiliation_strings":["[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113538042","display_name":"S. B. Manich","orcid":null},"institutions":[{"id":"https://openalex.org/I9617848","display_name":"Universitat Polit\u00e8cnica de Catalunya","ror":"https://ror.org/03mb6wj31","country_code":"ES","type":"education","lineage":["https://openalex.org/I9617848"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"S. B. Manich","raw_affiliation_strings":["[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]"],"affiliations":[{"raw_affiliation_string":"[Electrical Engineering dep. (EEL), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain]","institution_ids":["https://openalex.org/I9617848"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":1,"citation_normalized_percentile":{"value":0.230409,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":64,"max":71},"biblio":{"volume":null,"issue":null,"first_page":"244","last_page":"244"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9986,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9978,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-equipment","display_name":"Automatic test equipment","score":0.6323981},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.51230204},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42280555}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.68514025},{"id":"https://openalex.org/C141842801","wikidata":"https://www.wikidata.org/wiki/Q363815","display_name":"Automatic test equipment","level":3,"score":0.6323981},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6074519},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5236956},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.51230204},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.46081442},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43279883},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.42621198},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42280555},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41287088},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37929532},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26475787},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.25912967},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16138524},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/etsym.2010.5512749","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1548951997","https://openalex.org/W1923374043","https://openalex.org/W2061326683","https://openalex.org/W2112392595","https://openalex.org/W2113139456","https://openalex.org/W2115170364","https://openalex.org/W2126180182","https://openalex.org/W2134869803","https://openalex.org/W2153201966","https://openalex.org/W2397058827","https://openalex.org/W581407999"],"related_works":["https://openalex.org/W4200391368","https://openalex.org/W2978161533","https://openalex.org/W2379338802","https://openalex.org/W2370066713","https://openalex.org/W2355315220","https://openalex.org/W2111241003","https://openalex.org/W2091330445","https://openalex.org/W1984979050","https://openalex.org/W1979131826","https://openalex.org/W1844013954"],"abstract_inverted_index":{"Summary":[0],"form":[1],"of":[2,56,67,136,143,150],"the":[3,53,57,59,64,68,92,94,99,130,137,141,144,151],"only":[4],"given:":[5],"The":[6,26,133],"paper":[7],"presents":[8],"an":[9,13],"IP":[10],"module":[11,27],"containing":[12],"L-ATE":[14],"(IPATE)":[15],"able":[16],"to":[17,116],"conduct":[18],"digital":[19,54,138],"test":[20,29,131],"at":[21],"a":[22,36,103,118],"very":[23],"low":[24,81],"cost.":[25],"sends":[28],"vectors":[30],"and":[31,48,72,77],"analyzes":[32],"output":[33],"responses":[34],"through":[35,102],"one":[37,112],"bit":[38],"bidirectional":[39],"synchronous":[40],"channel,":[41],"as":[42,44],"well":[43],"performing":[45],"standard":[46],"flow":[47],"shmoo":[49],"tests.":[50],"Apart":[51],"from":[52,98],"information":[55],"test,":[58],"IP-ATE":[60,100],"system":[61,101,145],"can":[62,108,122],"control":[63],"following":[65],"parameters":[66],"DUT:":[69],"clock":[70],"frequency":[71],"phase,":[73],"capture":[74],"cycle":[75],"delay":[76],"supply":[78,88,95],"voltage.":[79],"A":[80],"cost,":[82],"customer":[83],"specific":[84],"external":[85],"programmable":[86],"power":[87],"was":[89],"designed":[90],"for":[91],"controlling":[93],"voltage":[96],"commanded":[97],"bus":[104],"interface.":[105],"Several":[106],"IPATEs":[107],"be":[109],"synthesized":[110],"in":[111,126],"or":[113,125],"more":[114],"FPGAs":[115],"create":[117],"multisite":[119],"tester.":[120],"They":[121],"operate":[123],"independently":[124],"cooperation,":[127],"depending":[128],"on":[129],"needs.":[132],"fail-safe":[134],"design":[135],"part":[139],"makes":[140],"operation":[142],"robust":[146],"against":[147],"catastrophic":[148],"failures":[149],"FPGA.":[152]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W1981630413","counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2024-12-07T18:00:35.562011","created_date":"2016-06-24"}