乐胖代购免代理版

{"id":"https://openalex.org/W2108066628","doi":"https://doi.org/10.1109/dsd.2009.237","title":"An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions","display_name":"An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions","publication_year":2009,"publication_date":"2009-08-01","ids":{"openalex":"https://openalex.org/W2108066628","doi":"https://doi.org/10.1109/dsd.2009.237","mag":"2108066628"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2009.237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013237315","display_name":"Salvador Petit","orcid":"https://orcid.org/0000-0003-2426-4134"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Salvador Petit","raw_affiliation_strings":["Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062237691","display_name":"Rafael Ubal","orcid":null},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Rafael Ubal","raw_affiliation_strings":["Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044390347","display_name":"Julio Sahuquillo","orcid":"https://orcid.org/0000-0001-8630-4846"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Sahuquillo","raw_affiliation_strings":["Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101612028","display_name":"Pedro L\u00f3pez","orcid":"https://orcid.org/0000-0003-4544-955X"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Lopez","raw_affiliation_strings":["Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040384183","display_name":"J. Duato","orcid":"https://orcid.org/0000-0002-7785-0607"},"institutions":[{"id":"https://openalex.org/I60053951","display_name":"Universitat Polit\u00e8cnica de Val\u00e8ncia","ror":"https://ror.org/01460j859","country_code":"ES","type":"education","lineage":["https://openalex.org/I60053951"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Jose Duato","raw_affiliation_strings":["Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain"],"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Eng. (DISCA), Univ. Politec. de Valencia, Valencia, Spain","institution_ids":["https://openalex.org/I60053951"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.336,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":3,"citation_normalized_percentile":{"value":0.443742,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":74,"max":77},"biblio":{"volume":null,"issue":null,"first_page":"635","last_page":"642"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9988,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9984,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.8650793},{"id":"https://openalex.org/keywords/out-of-order-execution","display_name":"Out-of-order execution","score":0.6820414},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.62480116},{"id":"https://openalex.org/keywords/commit","display_name":"Commit","score":0.6225669},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5827},{"id":"https://openalex.org/keywords/branch-predictor","display_name":"Branch predictor","score":0.46576834},{"id":"https://openalex.org/keywords/speculative-execution","display_name":"Speculative execution","score":0.43389714}],"concepts":[{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.8650793},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.76723933},{"id":"https://openalex.org/C1793878","wikidata":"https://www.wikidata.org/wiki/Q1153762","display_name":"Out-of-order execution","level":2,"score":0.6820414},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.62480116},{"id":"https://openalex.org/C153180980","wikidata":"https://www.wikidata.org/wiki/Q19776675","display_name":"Commit","level":2,"score":0.6225669},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5827},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.56597984},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.53954786},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47353074},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.46646273},{"id":"https://openalex.org/C168522837","wikidata":"https://www.wikidata.org/wiki/Q679552","display_name":"Branch predictor","level":2,"score":0.46576834},{"id":"https://openalex.org/C47941915","wikidata":"https://www.wikidata.org/wiki/Q107885","display_name":"Speculation","level":2,"score":0.45218652},{"id":"https://openalex.org/C141331961","wikidata":"https://www.wikidata.org/wiki/Q2164465","display_name":"Speculative execution","level":2,"score":0.43389714},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.37310034},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.07947865},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/dsd.2009.237","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.43,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":22,"referenced_works":["https://openalex.org/W2032094184","https://openalex.org/W2105900173","https://openalex.org/W2112744811","https://openalex.org/W2112833506","https://openalex.org/W2118859527","https://openalex.org/W2118896605","https://openalex.org/W2123608497","https://openalex.org/W2125203708","https://openalex.org/W2137860371","https://openalex.org/W2143032080","https://openalex.org/W2147098645","https://openalex.org/W2153456949","https://openalex.org/W2161864047","https://openalex.org/W2296408112","https://openalex.org/W2542426564","https://openalex.org/W4232059819","https://openalex.org/W4236345830","https://openalex.org/W4241271647","https://openalex.org/W4241874262","https://openalex.org/W4242771098","https://openalex.org/W4244763500","https://openalex.org/W63944998"],"related_works":["https://openalex.org/W4250432526","https://openalex.org/W3194312717","https://openalex.org/W2897302968","https://openalex.org/W2745771918","https://openalex.org/W2434762079","https://openalex.org/W2139338109","https://openalex.org/W2111412181","https://openalex.org/W2101536355","https://openalex.org/W1916582918","https://openalex.org/W1595275176"],"abstract_inverted_index":{"Current":[0],"superscalar":[1],"processors":[2],"use":[3],"a":[4,33,44,56,100,105,112],"reorder":[5],"buffer":[6,61],"(ROB)":[7],"to":[8,28,82,111],"support":[9],"speculation,":[10],"precise":[11],"exceptions,":[12],"and":[13],"register":[14,78],"reclamation.":[15],"Instructions":[16],"are":[17,66],"retired":[18,67],"from":[19,63],"this":[20,42,83],"structure":[21,58],"in":[22],"program":[23],"order,":[24],"which":[25,51,64],"may":[26],"lead":[27],"significant":[29],"performance":[30,110],"degradation":[31],"if":[32],"long":[34],"latency":[35],"operation":[36],"blocks":[37],"the":[38,53,92,117],"ROB":[39,54],"head.":[40],"In":[41],"paper,":[43],"checkpoint-free":[45],"out-of-order":[46],"commit":[47],"architecture":[48],"is":[49,74,85,95],"proposed,":[50],"replaces":[52],"with":[55],"small":[57],"called":[59],"validation":[60],"(VB)":[62],"instructions":[65],"as":[68,70],"soon":[69],"their":[71],"speculative":[72],"state":[73],"resolved.":[75],"An":[76],"aggressive":[77],"reclamation":[79],"mechanism":[80],"targeted":[81],"microarchitecture":[84,94],"also":[86],"devised.":[87],"Experimental":[88],"results":[89],"show":[90],"that":[91],"VB":[93,107],"much":[96],"more":[97],"efficient":[98],"than":[99],"ROB-based":[101],"microprocessor.":[102],"For":[103],"example,":[104],"32-entry":[106],"provides":[108],"similar":[109],"256-entry":[113],"ROB,":[114],"while":[115],"reducing":[116],"utilization":[118],"of":[119],"other":[120],"major":[121],"processor":[122],"structures.":[123]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2108066628","counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2024-12-11T15:34:55.179674","created_date":"2016-06-24"}