乐胖代购免代理版

{"id":"https://openalex.org/W2127172509","doi":"https://doi.org/10.1109/delta.2002.994579","title":"Analog and mixed-signal IP cores testing","display_name":"Analog and mixed-signal IP cores testing","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2127172509","doi":"https://doi.org/10.1109/delta.2002.994579","mag":"2127172509"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/delta.2002.994579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103546306","display_name":"M.W.T. Wong","orcid":null},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"M.W.T. Wong","raw_affiliation_strings":["Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Kowloon, China"],"affiliations":[{"raw_affiliation_string":"Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Kowloon, China","institution_ids":["https://openalex.org/I14243506"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109196643","display_name":"K.Y. Ko","orcid":null},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"K.Y. Ko","raw_affiliation_strings":["The Hong Kong Polytechnic University#TAB#"],"affiliations":[{"raw_affiliation_string":"The Hong Kong Polytechnic University#TAB#","institution_ids":["https://openalex.org/I14243506"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112224447","display_name":"Y.S. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I14243506","display_name":"Hong Kong Polytechnic University","ror":"https://ror.org/0030zas98","country_code":"HK","type":"education","lineage":["https://openalex.org/I14243506"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Y.S. Lee","raw_affiliation_strings":["The Hong Kong Polytechnic University#TAB#"],"affiliations":[{"raw_affiliation_string":"The Hong Kong Polytechnic University#TAB#","institution_ids":["https://openalex.org/I14243506"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":0,"max":59},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9943,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.7471903},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.51020384},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.49588737}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.7471903},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.59994733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.57080406},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.51020384},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.49588737},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48095837},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4472507},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42747116},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.41956505},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39730248},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.30011302},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29621768},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2916046},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.22589356},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13086784},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/delta.2002.994579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.53,"id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1548728919","https://openalex.org/W1763985980","https://openalex.org/W1924406256","https://openalex.org/W2103943632","https://openalex.org/W2104548962","https://openalex.org/W2106816366","https://openalex.org/W2139531977","https://openalex.org/W2139591540","https://openalex.org/W2147084005","https://openalex.org/W2156213538","https://openalex.org/W2160070535"],"related_works":["https://openalex.org/W776711554","https://openalex.org/W2989159162","https://openalex.org/W2153201966","https://openalex.org/W2146381271","https://openalex.org/W2139513292","https://openalex.org/W2122754719","https://openalex.org/W2108140302","https://openalex.org/W1982569681","https://openalex.org/W1978339999","https://openalex.org/W1901574727"],"abstract_inverted_index":{"This":[0],"paper,":[1],"describes":[2],"a":[3,27,130],"test":[4,29,146],"approach":[5],"for":[6,56,156],"Intellectual":[7],"Property":[8],"(IP)":[9],"analog":[10],"or":[11],"mixed-signal":[12],"cores,":[13],"which":[14,63],"may":[15],"be":[16,65],"used":[17],"in":[18,44,67],"core-based":[19],"System-on-Chip":[20],"(SOC)":[21],"designs.":[22],"The":[23,48],"proposed":[24,118,150],"method":[25,76,103],"comprises":[26],"two-phase":[28],"design":[30],"process.":[31],"Given":[32],"an":[33,37,98,123],"analog/mixed-signal":[34],"IP":[35,161],"core,":[36],"equivalent":[38],"fault":[39,82,115],"analysis":[40],"is":[41,51,134,153],"carried":[42],"out":[43],"the":[45,58,68,86,91,106,117,139,143,149,157],"initial":[46],"phase.":[47,70],"main":[49],"aim":[50],"to":[52,64,79,85,96,136],"extract":[53],"useful":[54],"insights":[55],"improving":[57],"BIST":[59,119,151],"and":[60,128],"DfT":[61],"designs":[62],"conducted":[66],"second":[69,92],"An":[71],"early":[72],"built-in":[73],"self-test":[74],"(BIST)":[75],"was":[77],"able":[78],"achieve":[80],"high":[81,114],"coverage":[83],"comparable":[84],"traditional":[87],"scan":[88],"techniques.":[89],"In":[90],"phase,":[93],"we":[94],"propose":[95],"apply":[97],"improved":[99],"version":[100],"of":[101,109,142,160],"this":[102],"based":[104],"on":[105],"weighted":[107],"sum":[108],"selected":[110],"node":[111],"voltages.":[112],"Besides":[113],"coverage,":[116],"technique":[120,152],"only":[121,129],"needs":[122],"extra":[124],"testing":[125,158],"output":[126],"pin":[127],"single":[131],"DC":[132],"stimulus":[133],"needed":[135],"feed":[137],"at":[138],"primary":[140],"input":[141],"circuit":[144],"under":[145],"(CUT).":[147],"Hence,":[148],"especially":[154],"suitable":[155],"environment":[159],"cores.":[162]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2127172509","counts_by_year":[],"updated_date":"2024-12-10T11:37:48.581443","created_date":"2016-06-24"}