{"id":"https://openalex.org/W3149260006","doi":"https://doi.org/10.1109/date.2012.6176505","title":"Test generation for clock-domain crossing faults in integrated circuits","display_name":"Test generation for clock-domain crossing faults in integrated circuits","publication_year":2012,"publication_date":"2012-03-01","ids":{"openalex":"https://openalex.org/W3149260006","doi":"https://doi.org/10.1109/date.2012.6176505","mag":"3149260006"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176505","pdf_url":null,"source":{"id":"https://openalex.org/S4363608094","display_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079088715","display_name":"Naghmeh Karimi","orcid":"https://orcid.org/0000-0002-5825-6637"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"N. Karimi","raw_affiliation_strings":["Electrical & Computer Engineering Department, Duke University, Durham, NC, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering Department, Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033880864","display_name":"Krishnendu Chakrabarty","orcid":"https://orcid.org/0000-0003-4475-6435"},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Chakrabarty","raw_affiliation_strings":["Electrical & Computer Engineering Department, Duke University, Durham, NC, USA"],"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering Department, Duke University, Durham, NC, USA","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054728270","display_name":"Pallav Gupta","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Gupta","raw_affiliation_strings":["Test CAD Technology Group, Intel Corporation, Folsom, CA, USA"],"affiliations":[{"raw_affiliation_string":"Test CAD Technology Group, Intel Corporation, Folsom, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041464318","display_name":"S. Patil","orcid":"https://orcid.org/0009-0001-4860-3607"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Patil","raw_affiliation_strings":["SoC Enabling Group, Intel Corporation, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"SoC Enabling Group, Intel Corporation, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.383,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":7,"citation_normalized_percentile":{"value":0.792741,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":82,"max":83},"biblio":{"volume":"5","issue":null,"first_page":"406","last_page":"411"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9981,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5023432},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4935161},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35956967},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.34538424},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26660764},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18134871}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2012.6176505","pdf_url":null,"source":{"id":"https://openalex.org/S4363608094","display_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.59,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":10,"referenced_works":["https://openalex.org/W1520384708","https://openalex.org/W1761424569","https://openalex.org/W1971295415","https://openalex.org/W2014501931","https://openalex.org/W2057126586","https://openalex.org/W2069345435","https://openalex.org/W2119616711","https://openalex.org/W2129981070","https://openalex.org/W2171033415","https://openalex.org/W4235150798"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W4254560580","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2323083271","https://openalex.org/W2131559056","https://openalex.org/W2127167802","https://openalex.org/W2080984854","https://openalex.org/W2019500818"],"abstract_inverted_index":{"Clock-domain":[0],"crossing":[1],"(CDC)":[2],"faults":[3,80],"are":[4,25,85],"a":[5,46,70],"serious":[6],"concern":[7],"for":[8,41,87,139],"high-speed,":[9],"multi-core":[10],"integrated":[11],"circuits.":[12],"Even":[13],"when":[14],"robust":[15],"design":[16,22],"methods":[17,116],"based":[18],"on":[19],"synchronizers":[20],"and":[21,106],"verification":[23],"techniques":[24],"used,":[26],"process":[27],"variations":[28],"can":[29,125],"introduce":[30],"subtle":[31],"timing":[32],"problems":[33],"that":[34,50,91],"affect":[35],"data":[36,68],"transfer":[37],"across":[38],"clock-domain":[39,82],"boundaries":[40],"fabricated":[42],"chips.":[43],"We":[44,63],"present":[45,65],"test":[47],"generation":[48],"technique":[49],"leverages":[51],"commercial":[52,102],"ATPG":[53,105,115,132],"tools,":[54],"but":[55],"introduces":[56],"additional":[57],"constraints,":[58],"to":[59,74,135],"detect":[60,126],"CDC":[61,79,129,141],"faults.":[62,142],"also":[64],"HSpice":[66],"simulation":[67],"using":[69],"45":[71],"nm":[72],"technology":[73],"quantify":[75],"the":[76,99,107,112,122],"occurrence":[77],"of":[78,101,114],"at":[81],"boundaries.":[83],"Results":[84],"presented":[86],"synthesized":[88],"IWLS05":[89],"benchmarks":[90],"include":[92],"multiple":[93],"clock":[94],"domains.":[95],"The":[96],"results":[97],"highlight":[98],"ineffectiveness":[100],"transition-delay":[103],"fault":[104],"\"coverage":[108],"gap\"":[109],"resulting":[110],"from":[111],"use":[113],"employed":[117],"in":[118],"industry":[119],"today.":[120],"While":[121],"proposed":[123],"method":[124],"nearly":[127],"all":[128],"faults,":[130],"TDF":[131],"is":[133],"found":[134],"be":[136],"severely":[137],"deficient":[138],"screening":[140]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W3149260006","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2024-12-13T16:45:22.936799","created_date":"2021-04-13"}