乐胖代购免代理版

{"id":"https://openalex.org/W2169666835","doi":"https://doi.org/10.1109/date.2006.244000","title":"An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration","display_name":"An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W2169666835","doi":"https://doi.org/10.1109/date.2006.244000","mag":"2169666835"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2006.244000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091526399","display_name":"Federico Angiolini","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Angiolini","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070675875","display_name":"Jianjiang Ceng","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Ceng","raw_affiliation_strings":["Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023470562","display_name":"Rainer Leupers","orcid":"https://orcid.org/0000-0002-6735-3033"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"R. Leupers","raw_affiliation_strings":["Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Signal Processing Systems, RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015466734","display_name":"Federico Ferrari","orcid":"https://orcid.org/0000-0003-1563-9387"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Ferrari","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021455020","display_name":"Cesare Ferri","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C. Ferri","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043408422","display_name":"Luca Benini","orcid":"https://orcid.org/0000-0001-8068-3806"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Benini","raw_affiliation_strings":["Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informatica e Sistemistica, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.94,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":45,"citation_normalized_percentile":{"value":0.844939,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":92,"max":93},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7755313},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.76274025},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.47648498},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.41015998}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7755313},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.76274025},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6941638},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6833062},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.65442705},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.64679575},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5550921},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.47648498},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.47619238},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4277557},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.41015998},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/date.2006.244000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.66,"display_name":"Industry, innovation and infrastructure"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":15,"referenced_works":["https://openalex.org/W1532503506","https://openalex.org/W1585971644","https://openalex.org/W1600358781","https://openalex.org/W2000801758","https://openalex.org/W2062581063","https://openalex.org/W2090809553","https://openalex.org/W2111919017","https://openalex.org/W2139653418","https://openalex.org/W2144981359","https://openalex.org/W2146147106","https://openalex.org/W2161038820","https://openalex.org/W4237771018","https://openalex.org/W4244878519","https://openalex.org/W4247846214","https://openalex.org/W4252879211"],"related_works":["https://openalex.org/W4230718388","https://openalex.org/W2169248084","https://openalex.org/W2124403023","https://openalex.org/W211156700","https://openalex.org/W2057268231","https://openalex.org/W2051542972","https://openalex.org/W2016843712","https://openalex.org/W2002682434","https://openalex.org/W1973069902","https://openalex.org/W1970446888"],"abstract_inverted_index":{"In":[0],"recent":[1],"years,":[2],"increasing":[3],"manufacturing":[4],"density":[5],"has":[6],"allowed":[7],"the":[8,24,44,57,62,93,99,105],"development":[9],"of":[10,23,46,59,114],"Multi-Processor":[11],"Systems-on-Chip":[12],"(MPSoCs).":[13],"Application-Specific":[14],"Instruction":[15],"Set":[16],"Processors":[17],"(ASIPs)":[18],"stand":[19],"out":[20],"as":[21,34],"one":[22],"most":[25],"efficient":[26],"design":[27,63,115],"paradigms":[28],"and":[29,49,74,97,110],"could":[30],"be":[31,52],"especially":[32],"effective":[33],"SoC":[35,47],"computing":[36],"engines.":[37],"However,":[38],"multiple":[39],"hurdles":[40],"which":[41],"are":[42],"hindering":[43],"productivity":[45],"designers":[48],"researchers":[50],"must":[51],"solved":[53],"first.":[54],"Among":[55],"them,":[56],"difficulty":[58],"thoroughly":[60],"exploring":[61],"space":[64,116],"by":[65,82],"simultaneously":[66],"sweeping":[67],"axes":[68],"like":[69],"processing":[70],"elements,":[71],"memory":[72],"hierarchies":[73],"chip":[75],"interconnect":[76],"fabrics.":[77],"We":[78],"tackle":[79],"this":[80],"challenge":[81],"proposing":[83],"an":[84],"integrated":[85],"approach":[86],"where":[87],"state-of-the-art":[88],"platform":[89],"modeling":[90],"infrastructures,":[91],"at":[92,98],"IP":[94],"core":[95],"level":[96],"system":[100],"level,":[101],"meet":[102],"to":[103],"provide":[104],"designer":[106],"with":[107],"maximum":[108],"openness":[109],"flexibility":[111],"in":[112],"terms":[113],"exploration.":[117]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2169666835","counts_by_year":[{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":3}],"updated_date":"2024-12-09T23:41:56.355117","created_date":"2016-06-24"}