乐胖代购免代理版

{"id":"https://openalex.org/W2124436379","doi":"https://doi.org/10.1109/cicc.2006.320984","title":"Design and implementation of a reconfigurable heterogeneous multiprocessor SoC","display_name":"Design and implementation of a reconfigurable heterogeneous multiprocessor SoC","publication_year":2006,"publication_date":"2006-09-01","ids":{"openalex":"https://openalex.org/W2124436379","doi":"https://doi.org/10.1109/cicc.2006.320984","mag":"2124436379"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2006.320984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112381215","display_name":"Massimo Bocchi","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Massimo Bocchi","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110891226","display_name":"Mario De Dominicis","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario De Dominicis","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045668159","display_name":"Claudio Mucci","orcid":"https://orcid.org/0000-0002-4660-207X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Claudio Mucci","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036359287","display_name":"Antonio Deledda","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Deledda","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070004082","display_name":"Fabio Campi","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Fabio Campi","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083656325","display_name":"Andrea Lodi","orcid":"https://orcid.org/0000-0001-9269-633X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Lodi","raw_affiliation_strings":["Adv. Res. Center on Electron. Syst., Bologna Univ."],"affiliations":[{"raw_affiliation_string":"Adv. Res. Center on Electron. Syst., Bologna Univ.","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057024890","display_name":"M. Toma","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mario Toma","raw_affiliation_strings":["ARCES, Advanced Research Center on Electronic Systems, University of Bologna, Italy; STMicroelectronics, FTM, Agrate Brianza, Italy"],"affiliations":[{"raw_affiliation_string":"ARCES, Advanced Research Center on Electronic Systems, University of Bologna, Italy; STMicroelectronics, FTM, Agrate Brianza, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040667886","display_name":"R. Guerrieri","orcid":"https://orcid.org/0000-0002-8601-6884"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Roberto Guerrieri","raw_affiliation_strings":["ARCES, Advanced Research Center on Electronic Systems, University of Bologna, Italy"],"affiliations":[{"raw_affiliation_string":"ARCES, Advanced Research Center on Electronic Systems, University of Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.196,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":4,"citation_normalized_percentile":{"value":0.504427,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":74,"max":76},"biblio":{"volume":null,"issue":null,"first_page":"93","last_page":"96"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.49251708},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable Computing","score":0.46131206},{"id":"https://openalex.org/keywords/symmetric-multiprocessor-system","display_name":"Symmetric multiprocessor system","score":0.45684326},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.42298055}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7888702},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.75546706},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.60577446},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.57956725},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.57750326},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.53018373},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.49251708},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.46131206},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.45684326},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.42298055},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.37860852},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35589558},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2006.320984","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":6,"referenced_works":["https://openalex.org/W1481838731","https://openalex.org/W1684229801","https://openalex.org/W2022111223","https://openalex.org/W2030922743","https://openalex.org/W2070392651","https://openalex.org/W2128602802"],"related_works":["https://openalex.org/W4385730960","https://openalex.org/W4382053335","https://openalex.org/W4376881175","https://openalex.org/W4364295250","https://openalex.org/W4310584696","https://openalex.org/W4237840813","https://openalex.org/W2993622674","https://openalex.org/W2538644970","https://openalex.org/W2128502296","https://openalex.org/W1833044483"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,12,16,30,41,46,50,56,64,68,73,78,112],"novel":[4],"heterogeneous":[5,42],"shared":[6],"memory":[7],"multiprocessor":[8],"architecture":[9,105],"based":[10],"on":[11,84,98],"reconfigurable":[13,31,38,57,65],"processor":[14,48],"and":[15],"standard":[17],"RISC":[18,47,69],"processor.":[19],"The":[20,102],"work":[21,60],"aims":[22],"at":[23],"increasing":[24],"further":[25],"the":[26,34,37,99],"computational":[27,53,74],"density":[28,54,75],"of":[29,36,80],"device":[32],"by":[33,77],"integration":[35],"hardware":[39],"into":[40],"multi-core":[43,103],"architecture.":[44],"Though":[45],"has":[49],"lower":[51],"inner":[52],"than":[55],"processor,":[58],"this":[59,89],"demonstrates":[61],"that":[62],"coupling":[63],"core":[66,70],"to":[67,72,82,94],"leads":[71],"increase":[76],"factor":[79],"up":[81,93],"1.7times":[83],"signal":[85],"processing":[86],"applications.":[87,101],"Moreover,":[88],"approach":[90],"also":[91],"achieves":[92],"37%":[95],"energy":[96],"savings":[97],"same":[100],"SoC":[104],"was":[106],"implemented":[107],"in":[108],"0.13mum":[109],"technology,":[110],"achieving":[111],"166MHz":[113],"clock":[114],"frequency":[115],"with":[116],"an":[117],"average":[118],"340mW":[119],"power":[120],"consumption":[121]},"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2124436379","counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2024-12-09T19:59:12.487883","created_date":"2016-06-24"}