{"id":"https://openalex.org/W2117814846","doi":"https://doi.org/10.1109/aspdac.1998.669476","title":"A clock-gating method for low-power LSI design","display_name":"A clock-gating method for low-power LSI design","publication_year":2002,"publication_date":"2002-11-27","ids":{"openalex":"https://openalex.org/W2117814846","doi":"https://doi.org/10.1109/aspdac.1998.669476","mag":"2117814846"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.1998.669476","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"proceedings-article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1998/aspdac98/pdffiles/05c_3.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065435508","display_name":"Takeshi Kitahara","orcid":"https://orcid.org/0000-0001-7063-5122"},"institutions":[{"id":"https://openalex.org/I1292669757","display_name":"Toshiba (Japan)","ror":"https://ror.org/0326v3z14","country_code":"JP","type":"company","lineage":["https://openalex.org/I1292669757"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"T. Kitahara","raw_affiliation_strings":["Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan"],"affiliations":[{"raw_affiliation_string":"Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan","institution_ids":["https://openalex.org/I1292669757"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113451551","display_name":"F. Minami","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"F. Minami","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077565266","display_name":"Tetsuzo Ueda","orcid":"https://orcid.org/0000-0003-3615-4354"},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"T. Ueda","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030692253","display_name":"Kimiyoshi Usami","orcid":"https://orcid.org/0000-0002-8911-3313"},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"K. Usami","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063483559","display_name":"S. Nishio","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"S. Nishio","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113697147","display_name":"M. Murakata","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"M. Murakata","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110453708","display_name":"T. Mitsuhashi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127366","display_name":"Toshiba (South Korea)","ror":"https://ror.org/02mavrn48","country_code":"KR","type":"company","lineage":["https://openalex.org/I1292669757","https://openalex.org/I4210127366"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"T. Mitsuhashi","raw_affiliation_strings":["Toshiba,"],"affiliations":[{"raw_affiliation_string":"Toshiba,","institution_ids":["https://openalex.org/I4210127366"]}]}],"institution_assertions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.748,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":28,"citation_normalized_percentile":{"value":0.910104,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":89},"biblio":{"volume":null,"issue":null,"first_page":"307","last_page":"312"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9999,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.9308268},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.83243966},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.7909111},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6952869},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6389094},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.6227421},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.5243676},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4675675}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.9308268},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.90483844},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.83243966},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7909111},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6952869},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.68538785},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6389094},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.6227421},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.56928873},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.5243676},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5119029},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4675675},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.452785},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4421147},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.43096784},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43090397},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.4243153},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22106925},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21407303},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.12926319},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.1998.669476","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.551.8413","pdf_url":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1998/aspdac98/pdffiles/05c_3.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false}],"best_oa_location":{"is_oa":true,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.551.8413","pdf_url":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1998/aspdac98/pdffiles/05c_3.pdf","source":{"id":"https://openalex.org/S4306400349","display_name":"CiteSeer X (The Pennsylvania State University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_indexed_in_scopus":false,"is_core":false,"host_organization":"https://openalex.org/I130769515","host_organization_name":"Pennsylvania State University","host_organization_lineage":["https://openalex.org/I130769515"],"host_organization_lineage_names":["Pennsylvania State University"],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false},"sustainable_development_goals":[],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1539883310","https://openalex.org/W2043165230","https://openalex.org/W2096704875","https://openalex.org/W2139098514","https://openalex.org/W2144877556","https://openalex.org/W2156114993","https://openalex.org/W2169894205","https://openalex.org/W3138612623","https://openalex.org/W3144157169","https://openalex.org/W4256283453","https://openalex.org/W655690458"],"related_works":["https://openalex.org/W4249038728","https://openalex.org/W4247180033","https://openalex.org/W3013924136","https://openalex.org/W2559451387","https://openalex.org/W2171851068","https://openalex.org/W2169622190","https://openalex.org/W2143420037","https://openalex.org/W2109769979","https://openalex.org/W2088914741","https://openalex.org/W2040807843"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3],"automated":[4],"layout":[5,45],"design":[6,46],"technique":[7,47],"for":[8,17,29,39,59,71,96],"the":[9,27,44,60,72,85],"gated-clock":[10,18,30,56,80],"design.":[11],"Two":[12],"issues":[13],"must":[14],"be":[15,88],"considered":[16],"circuits":[19],"to":[20,25,35,48,77],"work":[21],"correctly.":[22],"One":[23],"is":[24,34],"minimize":[26],"skew":[28],"nets.":[31],"The":[32],"other":[33],"keep":[36],"timing":[37,64,94],"constraints":[38,65,95],"enable-logic":[40,97],"parts.":[41,98],"We":[42,54,74],"propose":[43],"taking":[49],"these":[50],"things":[51],"into":[52],"consideration.":[53],"developed":[55],"tree":[57],"synthesizer":[58],"first":[61],"issue,":[62],"and":[63,67],"generator":[66],"clock":[68],"delay":[69],"estimator":[70],"second.":[73],"applied":[75],"it":[76],"a":[78],"practical":[79],"circuit.":[81],"By":[82],"our":[83],"technique,":[84],"clock-skew":[86],"could":[87],"less":[89],"than":[90],"0.2":[91],"ns":[92],"keeping":[93]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2117814846","counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2025-02-17T09:51:02.877578","created_date":"2016-06-24"}