乐胖代购免代理版

{"id":"https://openalex.org/W2161094424","doi":"https://doi.org/10.1109/4.272090","title":"Dynamic computational blocks for bit-level systolic arrays","display_name":"Dynamic computational blocks for bit-level systolic arrays","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W2161094424","doi":"https://doi.org/10.1109/4.272090","mag":"2161094424"},"language":"en","primary_location":{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.272090","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false},"type":"article","type_crossref":"journal-article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007393900","display_name":"G.A. Jullien","orcid":"https://orcid.org/0009-0009-0911-2926"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G.A. Jullien","raw_affiliation_strings":["VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114376306","display_name":"William C. Miller","orcid":"https://orcid.org/0000-0003-3060-0210"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"W.C. Miller","raw_affiliation_strings":["VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009978530","display_name":"R. Grondin","orcid":"https://orcid.org/0009-0003-3744-2507"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R. Grondin","raw_affiliation_strings":["VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059285852","display_name":"L. Del Pup","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]},{"id":"https://openalex.org/I176714629","display_name":"Bell (Canada)","ror":"https://ror.org/00xdg8m59","country_code":"CA","type":"funder","lineage":["https://openalex.org/I176714629"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"L. Del Pup","raw_affiliation_strings":["Bell Northern Research Limited, Ottawa, ONT, Canada","VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Bell Northern Research Limited, Ottawa, ONT, Canada","institution_ids":["https://openalex.org/I176714629"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082543333","display_name":"S.S. Bizzan","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S.S. Bizzan","raw_affiliation_strings":["VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5115601773","display_name":"Dapeng Zhang","orcid":"https://orcid.org/0000-0001-7349-8709"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"funder","lineage":["https://openalex.org/I74413500"]},{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"funder","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"None Dapeng Zhang","raw_affiliation_strings":["VLSI Research Group, University of Waterloo, Waterloo, ONT, Canada","VLSI Research Group, University of Windsor, Windsor, ONT, Canada"],"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"VLSI Research Group, University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institution_assertions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.278,"has_fulltext":true,"fulltext_origin":"ngrams","cited_by_count":19,"citation_normalized_percentile":{"value":0.75064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":84,"max":85},"biblio":{"volume":"29","issue":"1","first_page":"14","last_page":"22"},"is_retracted":false,"is_paratext":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.697451},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.51430357},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.50085235},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.43260944},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42804402},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.42029214},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.4169972},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.26621008},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12148744},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11555046},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09038791},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"is_oa":false,"landing_page_url":"https://doi.org/10.1109/4.272090","pdf_url":null,"source":{"id":"https://openalex.org/S83637746","display_name":"IEEE Journal of Solid-State Circuits","issn_l":"0018-9200","issn":["0018-9200","1558-173X"],"is_oa":false,"is_in_doaj":false,"is_indexed_in_scopus":true,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.42,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"grants":[],"datasets":[],"versions":[],"referenced_works_count":11,"referenced_works":["https://openalex.org/W1984588379","https://openalex.org/W2002467012","https://openalex.org/W2029156468","https://openalex.org/W2068355008","https://openalex.org/W2080267935","https://openalex.org/W2085156654","https://openalex.org/W2103490953","https://openalex.org/W2138134203","https://openalex.org/W2140149395","https://openalex.org/W2141307564","https://openalex.org/W2179451952"],"related_works":["https://openalex.org/W4312283151","https://openalex.org/W3104163240","https://openalex.org/W3008693296","https://openalex.org/W2760721665","https://openalex.org/W2381158465","https://openalex.org/W2359178629","https://openalex.org/W2136583354","https://openalex.org/W2111238207","https://openalex.org/W2029210135","https://openalex.org/W1995889332"],"abstract_inverted_index":{"Integrated":[0],"dynamic":[1,28],"logic":[2,57,82],"trees":[3,83],"with":[4,37],"latches":[5],"provide":[6],"cost":[7],"effective":[8],"circuit":[9,39],"techniques":[10,78],"for":[11,51,66,79],"building":[12],"massively":[13],"pipelined,":[14],"systolic,":[15],"computational":[16],"blocks":[17],"operating":[18],"at":[19],"the":[20,80,98],"bit":[21],"level.":[22],"Recent":[23],"results":[24,70],"have":[25],"demonstrated":[26],"that":[27],"pipelines":[29],"are":[30,86,94],"capable":[31],"of":[32,48,55],"very":[33],"high":[34,65],"switching":[35],"speeds":[36],"appropriate":[38],"design":[40],"techniques.":[41],"In":[42],"this":[43,49],"paper":[44],"we":[45],"trade":[46],"some":[47],"speed":[50],"much":[52],"higher":[53],"functionality":[54],"each":[56],"block.":[58],"The":[59],"resulting":[60],"throughput":[61],"rate":[62],"remains":[63],"sufficiently":[64],"useful":[67],"applications,":[68],"but":[69],"in":[71],"substantial":[72],"area":[73],"and":[74],"power":[75],"savings.":[76],"Design":[77],"individual":[81],"(switching":[84],"trees)":[85],"based":[87],"on":[88],"simple":[89],"graph":[90],"theoretic":[91],"rules.":[92],"Examples":[93],"shown":[95],"to":[96],"support":[97],"technique.<":[99],">":[102]},"abstract_inverted_index_v3":null,"cited_by_api_url":"https://api.openalex.org/works?filter=cites:W2161094424","counts_by_year":[],"updated_date":"2025-03-22T23:20:56.084661","created_date":"2016-06-24"}