{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,28]],"date-time":"2024-11-28T19:10:10Z","timestamp":1732821010377,"version":"3.30.0"},"reference-count":32,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2024,9,25]],"date-time":"2024-09-25T00:00:00Z","timestamp":1727222400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems"],"abstract":"This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal Verification Methodology. Generative artificial intelligence, such as ChatGPT, demonstrated its ability to produce accurate and valuable assertions by employing text-based prompts and image-fed inputs, significantly reducing the required manual effort. This research presents a way of generating System Verilog assertions using the ChatGPT prompt, presenting an image to the Large Language Models, and requesting the assertions needed for the respective protocol. This approach shows the potential for artificial intelligence to revolutionize functional verification by automating complex tasks, ultimately ensuring faster and more reliable System-on-Chip development. The assertions generated by the Large Language Models are integrated into an existing Advance Peripheral Bus verification environment. This process involves running the assertions on a free EDA Playground platform with all three simulators (Cadence Incisive, Mentor Questa, and Synopsys Verilog Compiler Simulator). The main conclusions are that using ChatGPT-4.0 for generating System Verilog assertions significantly reduces the time and effort required for functional verification, demonstrating its potential to enhance efficiency and accuracy in verifying complex System-on-Chip designs.<\/jats:p>","DOI":"10.3390\/systems12100390","type":"journal-article","created":{"date-parts":[[2024,9,25]],"date-time":"2024-09-25T20:16:37Z","timestamp":1727295397000},"page":"390","source":"Crossref","is-referenced-by-count":0,"title":["Generative AI Assertions in UVM-Based System Verilog Functional Verification"],"prefix":"10.3390","volume":"12","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-9760-6169","authenticated-orcid":false,"given":"Valentin","family":"Radu","sequence":"first","affiliation":[{"name":"Faculty of Economics, Valahia University of Targoviste, 130004 Targoviste, Romania"}]},{"given":"Diana","family":"Dranga","sequence":"additional","affiliation":[{"name":"Faculty of Electronics and Telecommunications, National University of Science and Technology Politehnica of Bucharest, 060042 Bucharest, Romania"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-3882-5062","authenticated-orcid":false,"given":"Catalin","family":"Dumitrescu","sequence":"additional","affiliation":[{"name":"Faculty of Electronics and Telecommunications, National University of Science and Technology Politehnica of Bucharest, 060042 Bucharest, Romania"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-3166-3192","authenticated-orcid":false,"given":"Alina Iuliana","family":"Tabirca","sequence":"additional","affiliation":[{"name":"Faculty of Economics, Valahia University of Targoviste, 130004 Targoviste, Romania"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-3407-8052","authenticated-orcid":false,"given":"Maria Cristina","family":"Stefan","sequence":"additional","affiliation":[{"name":"Faculty of Economics, Valahia University of Targoviste, 130004 Targoviste, Romania"}]}],"member":"1968","published-online":{"date-parts":[[2024,9,25]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"267","DOI":"10.4271\/12-03-04-0020","article-title":"Literature review of verification and validation activities of automated driving systems","volume":"3","author":"Wishart","year":"2020","journal-title":"SAE Int. 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