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{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,12]],"date-time":"2024-07-12T10:10:17Z","timestamp":1720779017571},"reference-count":24,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2021,5,6]],"date-time":"2021-05-06T00:00:00Z","timestamp":1620259200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"CONFISCA is the first generic SIMD-based software countermeasure that can concurrently resist against Side-Channel Attack (SCA) and Fault Injection (FI). Its promising strength is presented in a PRESENT cipher case study and compared to software-based Dual-rail with Pre-charge Logic concurrent countermeasure. It has lower overhead, wider usability, and higher protection. Its protection has been compared using Correlation Power Analysis, Welch\u2019s T-Test, Signal-to-Noise Ratio and Normalized Inter-Class Variance testing methods. CONFISCA can on-the-fly switch between its two modes of operation: The High-Performance and High-Security by having only one instance of the cipher. This gives us the flexibility to trade performance\/energy with security, based on the actual critical needs.<\/jats:p>","DOI":"10.3390\/cryptography5020013","type":"journal-article","created":{"date-parts":[[2021,5,8]],"date-time":"2021-05-08T02:36:24Z","timestamp":1620441384000},"page":"13","source":"Crossref","is-referenced-by-count":0,"title":["CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes"],"prefix":"10.3390","volume":"5","author":[{"given":"Ehsan","family":"Aerabi","sequence":"first","affiliation":[{"name":"School of Computer Engineering, Iran University of Science and Technology, Tehran 16846-13114, Iran"},{"name":"Grenoble INP, Laboratoire de Conception et d\u2019Int\u00e9gration des Syst\u00e8mes (LCIS), Universit\u00e9 Grenoble Alpes, 26902 Valence, France"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-3249-7667","authenticated-orcid":false,"given":"David","family":"H\u00e9ly","sequence":"additional","affiliation":[{"name":"Grenoble INP, Laboratoire de Conception et d\u2019Int\u00e9gration des Syst\u00e8mes (LCIS), Universit\u00e9 Grenoble Alpes, 26902 Valence, France"}]},{"given":"Cyril","family":"Bresch","sequence":"additional","affiliation":[{"name":"Grenoble INP, Laboratoire de Conception et d\u2019Int\u00e9gration des Syst\u00e8mes (LCIS), Universit\u00e9 Grenoble Alpes, 26902 Valence, France"}]},{"given":"Athanasios","family":"Papadimitriou","sequence":"additional","affiliation":[{"name":"Grenoble INP, Laboratoire de Conception et d\u2019Int\u00e9gration des Syst\u00e8mes (LCIS), Universit\u00e9 Grenoble Alpes, 26902 Valence, France"},{"name":"Department of Informatics, University of Piraeus, 18534 Piraeus, Greece"}]},{"given":"Mahdi","family":"Fazeli","sequence":"additional","affiliation":[{"name":"School of Computer Engineering, Iran University of Science and Technology, Tehran 16846-13114, Iran"}]}],"member":"1968","published-online":{"date-parts":[[2021,5,6]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Peeters, E. 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