{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,30]],"date-time":"2024-08-30T02:26:00Z","timestamp":1724984760553},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,1]]},"DOI":"10.23919\/date51398.2021.9474062","type":"proceedings-article","created":{"date-parts":[[2021,8,24]],"date-time":"2021-08-24T22:11:46Z","timestamp":1629843106000},"source":"Crossref","is-referenced-by-count":2,"title":["Duetto: Latency Guarantees at Minimal Performance Cost"],"prefix":"10.23919","author":[{"given":"Reza","family":"Mirosanlou","sequence":"first","affiliation":[]},{"given":"Mohamed","family":"Hassan","sequence":"additional","affiliation":[]},{"given":"Rodolfo","family":"Pellizzoni","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Macsim: A cpu-gpu heterogeneous simulation framework user guide","author":"kim","year":"2012","journal-title":"Georgia Institute of Technology"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2007.34"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2014.6925998"},{"key":"ref13","article-title":"Wcet derivation under single core equivalence with explicit memory budget assignment","author":"mancuso","year":"0","journal-title":"Euromicro Conference on Real-Time Systems (ECRTS)"},{"key":"ref14","author":"standard","year":"2007","journal-title":"JEDEC JESD79–4B"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.24"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.3008288"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2011.28"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2018.00059"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS48715.2020.00-15"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RTSS.2013.44"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2857379"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461327"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"ref1","article-title":"Performance analysis of high-speed digital buses for multiprocessing systems","author":"bain","year":"0","journal-title":"ACM Annual symposium on Computer Architecture (ISCA)"},{"key":"ref9","article-title":"Amba axi protocol specification v2. 0","year":"2010","journal-title":"ARM Holdings"}],"event":{"name":"2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)","location":"Grenoble, France","start":{"date-parts":[[2021,2,1]]},"end":{"date-parts":[[2021,2,5]]}},"container-title":["2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9473901\/9473226\/09474062.pdf?arnumber=9474062","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T21:39:07Z","timestamp":1643319547000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9474062\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,1]]},"references-count":17,"URL":"https:\/\/doi.org\/10.23919\/date51398.2021.9474062","relation":{},"subject":[],"published":{"date-parts":[[2021,2,1]]}}}