{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,19]],"date-time":"2024-06-19T06:29:32Z","timestamp":1718778572567},"reference-count":21,"publisher":"Information Processing Society of Japan","issue":"0","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Information Processing"],"published-print":{"date-parts":[[2023]]},"DOI":"10.2197\/ipsjjip.31.495","type":"journal-article","created":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T22:13:55Z","timestamp":1692051235000},"page":"495-508","source":"Crossref","is-referenced-by-count":1,"title":["EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline"],"prefix":"10.2197","volume":"31","author":[{"given":"Senri","family":"Yoshikawa","sequence":"first","affiliation":[{"name":"University of Tsukuba"}]},{"given":"Shuji","family":"Sannomiya","sequence":"additional","affiliation":[{"name":"University of Tsukuba"}]},{"given":"Makoto","family":"Iwata","sequence":"additional","affiliation":[{"name":"Kochi University of Technology"}]},{"given":"Akira","family":"Sato","sequence":"additional","affiliation":[{"name":"University of Tsukuba"}]},{"given":"Hiroaki","family":"Nishikawa","sequence":"additional","affiliation":[{"name":"University of Tsukuba"}]}],"member":"1012","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] Terada, H., Miyata, S. and Iwata, M.: DDMP's: Self-Timed Super-Pipelined Data-Driven Multimedia Processors, Proc. IEEE<\/i>, Vol.87, pp.282-295 (1999).","DOI":"10.1109\/5.740021"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] Chang, Y., Huang, R. and Jiang, J.: Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits, Proc. IEEE International Symposium on Asynchronous Circuits and Systems<\/i> (ASYNC<\/i>), pp.19-26 (2019).","DOI":"10.1109\/ASYNC.2019.00011"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] Polzer, T. and Steininger, A.: An Approach for Efficient Metastability Characterization of FPGAs through the Designer, Proc. IEEE International Symposium on Asynchronous Circuits and Systems<\/i> (ASYNC<\/i>), pp.174-182 (2013).","DOI":"10.1109\/ASYNC.2013.14"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] Ho, Q.T., Rigaud, J.B., Fesquet, L., Renaudin, M. and Rolland, R.: Implementing asynchronous circuits on LUT based FPGAs, Proc. International Conference on Field Programmable Logic and Applications<\/i>, pp.36-46 (2002).","DOI":"10.1007\/3-540-46117-5_6"},{"key":"5","unstructured":"[5] Yoshikawa, S., Sannomiya, S., Iwata, M., Sato, A. and Nishikawa, H.: FPGA muki jikodoukigata paipurain kairo kouseihou [FPGA-Oriented Self-timed Pipeline Circuit Design Method], Information Processing Society of Japan SIG Technical Report, Vol.2021-ARC-243\/2021-SLDM-193, No.25, pp.1-7 (2021)."},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] Myers, J.C.: Asynchronous circuit design, University of Utah John Wiley & Sons, Inc. (2001).","DOI":"10.1002\/0471224146"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Vanbekbergen, P., Goossens, G., Catthoor, F. and Man, D.J.H.: Optimized synthesis of asynchronous control circuits from graph-theoretic specifications, IEEE Trans. Computer-aided Design of Integrated Circuits and Systems<\/i>, Vol.11, No.11, pp.1426-1438 (1992).","DOI":"10.1109\/43.177405"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] Oliveira, L.D., Bompean, D., Faria, A.L. and Oliveira, V.L.J.: Design of asynchronous systems on FPGA using direct mapping and synchronous specification, Proc. 2013 International Conference on Reconfigurable Computing and FPGAs<\/i> (ReConFig<\/i>), pp.1-6 (2013).","DOI":"10.1109\/ReConFig.2013.6732276"},{"key":"9","unstructured":"[9] Sokolov, D., Khomenko, V. and Mokhov, A.: Workcraft: Ten years later, This Asynchronous World, Essays Dedicated to Alex Yakovlev on the Occasion of his 60th Birthday<\/i>, pp.269-293 (2016)."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] Mannakkara, C. and Yoneda, T.: Asynchronous pipeline controller based on early acknowledgement protocol, IEICE Trans. Information and Systems<\/i>, Vol.93, No.8, pp.2145-2161 (2010).","DOI":"10.1587\/transinf.E93.D.2145"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] Takizawa, K., Hosaka, S. and Saito, H.: A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs, 2014 24th International Conference on Field Programmable Logic and Applications<\/i> (FPL<\/i>), pp.1-4 (2014).","DOI":"10.1109\/FPL.2014.6927435"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] Baz, A., Shang, D., Xia, F., Gu, X. and Yakovlev, A.: Energy efficiency of micropipelines under wide dynamic supply voltages, 2014 IEEE Faible Tension Faible Consommation<\/i>, pp.1-4 (2014).","DOI":"10.1109\/FTFC.2014.6828609"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] Tranchero, M. and Reyneri, M.L.: Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools<\/i>, pp.373-380 (2008).","DOI":"10.1109\/DSD.2008.73"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Bhardwaj, K., Mantovani, P., Carloni, P.L. and Nowick, M.S.: Towards a complete methodology for synthesizing bundled-data asynchronous circuits on FPGAs, Proc. 2019 IEEE\/ACM International Symposium on Low Power Electronics and Design<\/i> (ISLPED<\/i>), pp.1-6 (2019).","DOI":"10.1109\/ISLPED.2019.8824912"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] Mardari, A., Jel\u010dicov\u00e1, Z. and Spars\u00f8, J.: Design and FPGA-implementation of asynchronous circuits using two-phase handshaking, 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems<\/i> (ASYNC<\/i>), pp.9-18 (2019).","DOI":"10.1109\/ASYNC.2019.00010"},{"key":"16","unstructured":"[16] Furushima, J., Nakajima, M. and Saito, H.: Design of an Asynchronous Processor with Bundled-data Implementation on a Commercial Field Programmable Gate Array, Informatica<\/i>, Vol.40, pp.399-408 (2016)."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] Otake, T. and Saito, H.: A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints, IEICE Trans. Fundamentals of Electronics<\/i>, Vol.103, No.12, pp.1427-1436 (2020).","DOI":"10.1587\/transfun.2020VLP0006"},{"key":"18","unstructured":"[18] Sannomiya, S., Aoki, K., Iwata, M. and Nishikawa, H.: Power-performance Verification of Ultra-low-power Data-driven Networking Processor: ULP-CUE, Proc. 26th Int'l Conf. Parallel and Distributed Processing Techniques and Applications<\/i> (PDPTA<\/i>), pp.465-471 (2012)."},{"key":"19","unstructured":"[19] Sannomiya, S., Kagawa, N., Sakai, K. and Iwata, M.: A Data-Driven On-Chip Simulation Module and Its FPGA Implementation, Proc. Parallel and Distributed Processing Techniques and Applications<\/i> (PDPTA<\/i>), pp.710-716 (2008)."},{"key":"20","unstructured":"[20] Sannomiya, S., Omori, Y. and Iwata, M.: A Macroscopic Behavior Model for Self-timed Pipeline Systems, Proc. 17th Workshop on Parallel and Distributed Simulation<\/i> (PADS<\/i>), pp.133-140 (2003)."},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Nishikawa, H.: Design Philosophy of a Networking-oriented Data-driven Processor: CUE, IEICE Trans. Electronics<\/i>, Vol.E89-C, No.3, pp.221-229 (2006).","DOI":"10.1093\/ietele\/e89-c.3.221"}],"container-title":["Journal of Information Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/ipsjjip\/31\/0\/31_495\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,19]],"date-time":"2023-08-19T03:48:47Z","timestamp":1692416927000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/ipsjjip\/31\/0\/31_495\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023]]},"references-count":21,"journal-issue":{"issue":"0","published-print":{"date-parts":[[2023]]}},"URL":"https:\/\/doi.org\/10.2197\/ipsjjip.31.495","relation":{},"ISSN":["1882-6652"],"issn-type":[{"value":"1882-6652","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023]]}}}