{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,4,6]],"date-time":"2023-04-06T17:26:25Z","timestamp":1680801985400},"reference-count":25,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"12","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Inf. & Syst."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transinf.2016edp7090","type":"journal-article","created":{"date-parts":[[2016,11,30]],"date-time":"2016-11-30T17:14:12Z","timestamp":1480526052000},"page":"3072-3081","source":"Crossref","is-referenced-by-count":3,"title":["Performance Optimization of Light-Field Applications on GPU"],"prefix":"10.1587","volume":"E99.D","author":[{"given":"Yuttakon","family":"YUTTAKONKIT","sequence":"first","affiliation":[{"name":"Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology"}]},{"given":"Shinya","family":"TAKAMAEDA-YAMAZAKI","sequence":"additional","affiliation":[{"name":"Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology"}]},{"given":"Yasuhiko","family":"NAKASHIMA","sequence":"additional","affiliation":[{"name":"Computing Architecture Lab, Graduate School of Information Science, Nara Institute of Science and Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] S. \u212btolc, D. Soukup, B. Holl\u00e4nder, and R. Huber-M\u00f6rk, \u201cDepth and all-in-focus imaging by a multi-line-scan light-field camera,\u201d J. Electronic Imaging, vol.23, no.5, p.053020, 2014.","DOI":"10.1117\/1.JEI.23.5.053020"},{"key":"2","unstructured":"[2] C. Hern\u00e1ndez, \u201cLens blur in the new google camera app.\u201d Accessed: 2015-08-6."},{"key":"3","unstructured":"[3] R. Ng, M. Levoy, M. Br\u00e9dif, G. Duval, M. Horowitz, and P. Hanrahan, \u201cLight field photography with a hand-held plenoptic camera,\u201d Computer Science Technical Report CSTR, vol.2, no.11, 2005."},{"key":"4","unstructured":"[4] A. Lumsdaine, G. Chunev, and T. Georgiev, \u201cPlenoptic rendering with interactive performance using gpus,\u201d IS&T\/SPIE Electronic Imaging, pp.829513-829513, International Society for Optics and Photonics, 2012."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] J. Stratton, N. Anssari, C. Rodrigues, I.J. Sung, N. Obeid, L. Chang, G. Liu, and W. Hwu, \u201cOptimization and architecture effects on gpu computing workload performance,\u201d Innovative Parallel Computing (InPar), 2012, pp.1-10, May 2012.","DOI":"10.1109\/InPar.2012.6339605"},{"key":"6","unstructured":"[6] P. Micikevicius, \u201cGPU performance analysis and optimization,\u201d 2012."},{"key":"7","unstructured":"[7] NVIDIA, \u201cCuda C programming guide.\u201d Accessed: 2015-11-30."},{"key":"8","unstructured":"[8] T. Zinsser and B. Keck, \u201cSystematic performance optimization of cone-beam back-projection on the kepler architecture,\u201d Proc. 12th Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine, pp.225-228, 2013."},{"key":"9","unstructured":"[9] N. Maruyama and T. Aoki, \u201cOptimizing stencil computations for nvidia kepler gpus,\u201d Proc. 1st International Workshop on High-Performance Stencil Computations, pp.89-95, Vienna, 2014."},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Lee, S.J. Min, and R. Eigenmann, \u201cOpenMP to GPGPU: A compiler framework for automatic translation and optimization,\u201d SIGPLAN Not., vol.44, no.4, pp.101-110, Feb. 2009.","DOI":"10.1145\/1594835.1504194"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] M. Bauer, H. Cook, and B. Khailany, \u201cCudadma: optimizing gpu memory bandwidth via warp specialization,\u201d Proc. 2011 international conference for high performance computing, networking, storage and analysis, p.12, ACM, 2011.","DOI":"10.1145\/2063384.2063400"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] D. Lee, I. Dinov, B. Dong, B. Gutman, I. Yanovsky, and A.W. Toga, \u201cCuda optimization strategies for compute-and memory-bound neuroimaging algorithms,\u201d Computer methods and programs in biomedicine, vol.106, no.3, pp.175-187, 2012.","DOI":"10.1016\/j.cmpb.2010.10.013"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] W. Abu-Sufah and A.A. Karim, \u201cAuto-tuning of sparse matrix-vector multiplication on graphics processors,\u201d Supercomputing, pp.151-164, Springer, 2013.","DOI":"10.1007\/978-3-642-38750-0_12"},{"key":"14","unstructured":"[14] C. Perwass, \u201cThe next generation of photography,\u201d White Paper, www.raytrix.de."},{"key":"15","unstructured":"[15] Lytro, \u201cLytro Illum specification.\u201d Accessed: 2015-12-05."},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] T. Georgiev and A. Lumsdaine, \u201cFocused plenoptic camera and rendering,\u201d J. Electronic Imaging, vol.19, no.2, p.021106, 2010.","DOI":"10.1117\/1.3442712"},{"key":"17","unstructured":"[17] NVIDIA, \u201cParallel thread exuction ISA application guide.\u201d Accessed: 2015-11-30."},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] G.S. Murthy, M. Ravishankar, M.M. Baskaran, and P. Sadayappan, \u201cOptimal loop unrolling for gpgpu programs,\u201d 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), pp.1-11, IEEE, 2010.","DOI":"10.1109\/IPDPS.2010.5470423"},{"key":"19","unstructured":"[19] NVIDIA, \u201cCuda sample program.\u201d Accessed: 2015-11-30."},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] NVIDIA, \u201cMaxwell tuning guide,\u201d 2012. Accessed: 2015-12-10.","DOI":"10.1002\/wilm.10125"},{"key":"21","unstructured":"[21] P. Bialas and A. Strzelecki, \u201cBenchmarking the cost of thread divergence in cuda,\u201d arXiv preprint arXiv:1504.01650, 2015."},{"key":"22","unstructured":"[22] U.B. Vasily Volkov, \u201cBetter performance at lower occupancy.\u201d Accessed: 2016-6-8."},{"key":"23","unstructured":"[23] NVIDIA, \u201cNvidia gameworks, nvidia nsight visual studio edition, pipe utilization.\u201d Accessed: 2016-6-8."},{"key":"24","unstructured":"[24] N. TONY SCUDIERO, \u201cGPU memory bootcamp II: Beyond best practices.\u201d Accessed: 2016-6-8."},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] F. Winter, M. Clark, R. Edwards, and B. Joo, \u201cA framework for lattice QCD calculations on GPUs,\u201d Parallel and Distributed Processing Symposium, 2014 IEEE 28th International, pp.1073-1082, May 2014.","DOI":"10.1109\/IPDPS.2014.112"}],"container-title":["IEICE Transactions on Information and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016EDP7090\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,15]],"date-time":"2019-09-15T23:56:14Z","timestamp":1568591774000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transinf\/E99.D\/12\/E99.D_2016EDP7090\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":25,"journal-issue":{"issue":"12","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transinf.2016edp7090","relation":{},"ISSN":["0916-8532","1745-1361"],"issn-type":[{"value":"0916-8532","type":"print"},{"value":"1745-1361","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}