{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,28]],"date-time":"2022-03-28T22:14:32Z","timestamp":1648505672231},"reference-count":19,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"8","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transele.e99.c.974","type":"journal-article","created":{"date-parts":[[2016,7,31]],"date-time":"2016-07-31T22:12:06Z","timestamp":1470003126000},"page":"974-983","source":"Crossref","is-referenced-by-count":2,"title":["Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology"],"prefix":"10.1587","volume":"E99.C","author":[{"given":"Tian","family":"WANG","sequence":"first","affiliation":[{"name":"Institute of Microelectronics, Peking University"}]},{"given":"Xiaoxin","family":"CUI","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Peking University"}]},{"given":"Kai","family":"LIAO","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Peking University"}]},{"given":"Nan","family":"LIAO","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Peking University"}]},{"given":"Xiaole","family":"CUI","sequence":"additional","affiliation":[{"name":"Key Lab of Integrated Microsystems, Peking University Shenzhen Graduate School"}]},{"given":"Dunshan","family":"YU","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Peking University"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] Y.K. Choi, K. Asano, N. Lindert, and V. Subramanian, \u201cUltra-thin body SOI MOSFET for deep-sub-tenth micron era,\u201d Proc. IEEE International Electron Devices Meeting, pp.919-921, 1999."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] C. Gallon, C. Fenouillet-Beranger, A. Vandooren, F. Boeuf, S.Monfray, F. Payet, S. Orain, V. Fiori, F. Salvetti, N. Loubet, C.Charbuillet, A. Toffoli, F. Allain, K. Romanjek, I. Cayrefourcq, B. Ghyselen, C. Mazure, D. Delille, F. Judong, C. Perrot, M. Hopstaken, P. Scheblin, P. Rivallin, L. Brevard, O. Faynot, S. Cristoloveanu, and T. Skotnicki, \u201cUltra-thin fully depleted SOI devices with thin BOX, ground plane and strained liner booster,\u201d Proc. 2006 IEEE International SOI Conference, pp.17-18, 2006.","DOI":"10.1109\/SOI.2006.284410"},{"key":"3","unstructured":"[3] E. Yu, L. Chang, S. Ahmed, et al., \u201cFinFET scaling to 10 nm gate length,\u201d Proc. 2002 IEEE International Electron Devices Meeting, pp.251-254, 2002."},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] P. Mishra, A. Muttreja, and N.K. Jha, \u201cFinFET circuit design,\u201d in Nanoelectronic Circuit Design, pp.23-54, Springer New York, 2011.","DOI":"10.1007\/978-1-4419-7609-3_2"},{"key":"5","unstructured":"[5] D. Baccarin, D. Esseni, and M. Alioto, \u201cMixed FBB\/RBB: a novel low-leakage technique for FinFET forced stacks,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.20, no.8, pp.1467-1472, 2012."},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] D. Baccarin, D. Esseni, and M. Alioto, \u201cA novel back-biasing low-leakage technique for FinFET forced stacks,\u201d Proc. 2011 IEEE International Symp on Circuits and Systems, pp.2079-2082, Rio de Janeiro, 2011.","DOI":"10.1109\/ISCAS.2011.5938007"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] D. Baccarin, D. Esseni, and M. Alioto, \u201cLow-standby current 4T FinFET buffers: Analysis and evaluation below 45 nm,\u201d Proc. 2010 IEEE International Conference on Microelectronics, pp.296-299, 2010.","DOI":"10.1109\/ICM.2010.5696143"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] M.C. Johnson, D. Somasekhar, and K. Roy, \u201cLeakage control with efficient use of transistor stacks in single threshold CMOS,\u201d Proc. 36th annual ACM\/IEEE Design Automation Conference, pp.442-445, 1999.","DOI":"10.1109\/DAC.1999.781357"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] J.W. Tschanz, S.G. Narendra, Y. Ye, B.A. Bloechel, S. Borkar, and V. De, \u201cDynamic sleep transistor and body bias for active leakage power control of microprocessors,\u201d IEEE J. Solid-State Circuits, vol.38, no.11, pp.1838-1845, 2003.","DOI":"10.1109\/JSSC.2003.818291"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] S. Narendra, V. De, D. Antoniadis, A. Chandrakasan, and S. Borkar, \u201cScaling of stack effect and its application for leakage reduction,\u201d Proc. 2001 International symposium on Low power electronics and design, pp.195-200, 2001.","DOI":"10.1145\/383082.383132"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] V. De, \u201cLeakage-tolerant design techniques for high performance processors,\u201d Proc. 2002 international symposium on Physical design, p.28, 2002.","DOI":"10.1145\/505388.505396"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] K. Liao, X.X. Cui, N. Liao, K. Ma, D. Wu, W. Wei, R. Li, and D. Yu, \u201cUltra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs,\u201d Science China Information Science, vol.04, pp.1-13, 2014.","DOI":"10.1007\/s11432-013-4784-y"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] N. Liao, X.X. Cui, K. Liao, K. Ma, D. Wu, W. Wei, R. Li, and D. Yu, \u201cLow power adiabatic logic based on FinFETs,\u201d Science China Information Science, vol.57, no.2, pp.1-13, 2014.","DOI":"10.1007\/s11432-013-4902-x"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] K.S. Ma, X.X. Cui, K. Liao, et al., \u201cKey characterization factors of accurate power modeling for FinFET circuits,\u201d Sciece China Information Sciences, vol.58, no.2, pp.1-13, 2015.","DOI":"10.1007\/s11432-014-5169-6"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K. Liao, X.X. Cui, N. Liao, and K. Ma, \u201cLeakage Power Reduction of Adiabatic Circuits Based on FinFET Devices,\u201d IEICE Trans. Electron., vol.E96-C, no.8, pp.1068-1075, 2013.","DOI":"10.1587\/transele.E96.C.1068"},{"key":"16","unstructured":"[16] Predictive Technology Model ( http:\/\/ptm.asu.edu\/ ). Nanoscale Integration and Modeling (NIMO) Group, ASU."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Alioto, \u201cComparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.19, no.5, pp.751-762, 2011.","DOI":"10.1109\/TVLSI.2010.2040094"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] S. Narendra, V. De, S. Borkar, D.A. Antoniadis, and A.P.Chandrakasan, \u201cFull-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-\u00b5m CMOS,\u201d IEEE J. Solid-State Circuits, vol.39, no.3, pp.501-510, 2004.","DOI":"10.1109\/JSSC.2003.821776"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] N. Yadav, S. Dutt, M. Pattnaik, et al., \u201cDouble-gate FinFET process variation aware 10T SRAM cell topology design and analysis,\u201d IEEE European Conference on Circuit Theory and Design, 2013.","DOI":"10.1109\/ECCTD.2013.6662215"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E99.C\/8\/E99.C_974\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,12]],"date-time":"2019-09-12T00:14:05Z","timestamp":1568247245000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E99.C\/8\/E99.C_974\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":19,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e99.c.974","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}