{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T03:02:10Z","timestamp":1648522930088},"reference-count":28,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2016]]},"DOI":"10.1587\/transele.e99.c.623","type":"journal-article","created":{"date-parts":[[2016,5,31]],"date-time":"2016-05-31T22:11:18Z","timestamp":1464732678000},"page":"623-631","source":"Crossref","is-referenced-by-count":0,"title":["Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC"],"prefix":"10.1587","volume":"E99.C","author":[{"given":"Zhijie","family":"CHEN","sequence":"first","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology"}]},{"given":"Masaya","family":"MIYAHARA","sequence":"additional","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology"}]},{"given":"Akira","family":"MATSUZAWA","sequence":"additional","affiliation":[{"name":"Department of Physical Electronics, Tokyo Institute of Technology"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"crossref","unstructured":"[1] D. Binkley, \u201cTradeoffs and optimization in analog CMOS design,\u201d International Conference on Mixed Design of Integrated Circuits and Systems, pp.47-60, June 2007.","DOI":"10.1109\/MIXDES.2007.4286119"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Suryagandh, M. Garg, and J. Woo, \u201cA device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs,\u201d IEEE Trans. Electron Devices, vol.51, no.7, pp.1122-1128, July 2004.","DOI":"10.1109\/TED.2004.829872"},{"key":"3","unstructured":"[3] M. Bucher, G. Diles, and N. Makris, \u201cAnalog performance of advanced CMOS in weak, moderate, and strong inversion,\u201d International Conference Mixed Design of Integrated Circuits and Systems, pp.54-57, June 2010."},{"key":"4","unstructured":"[4] F. Maloberti, Data Converters, 1st ed., Springer US, 2007."},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] M. Miyahara and A. Matsuzawa, \u201cThe effects of switch resistances on pipelined ADC performances and the optimization for the settling time,\u201d IEICE Trans. Electronics, vol.E90-C, no.6, pp.1165-1171, June 2007.","DOI":"10.1093\/ietele\/e90-c.6.1165"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] J. Shen and P. Kinget, \u201cA 0.5-V 8-bit 10-Ms\/s pipelined ADC in 90-nm CMOS,\u201d IEEE J. Solid-State Circuits, vol.43, no.4, pp.787-795, April 2008.","DOI":"10.1109\/JSSC.2008.917470"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] Y. Miyahara, M. Sano, K. Koyama, T. Suzuki, K. Hamashita, and B.S. Song, \u201cA 14b 60 MS\/s pipelined ADC adaptively cancelling opamp gain and nonlinearity,\u201d IEEE J. Solid-State Circuits, vol.49, no.2, pp.416-425, Feb. 2014.","DOI":"10.1109\/JSSC.2013.2289902"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] L. Liu, D. Li, L. Chen, Y. Ye, and Z. Wang, \u201cA 1-V 15-bit audio \u0394 \u03a3-ADC in 0.18 \u00b5m CMOS,\u201d IEEE Trans. Circuits Syst. I: Reg. Papers, vol.59, no.5, pp.915-925, May 2012.","DOI":"10.1109\/TCSI.2012.2188949"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] S.C. Lee and Y. Chiu, \u201cA 15-MHz bandwidth 1-0 MASH \u03a3 \u0394 ADC with nonlinear memory error calibration achieving 85-dBc SFDR,\u201d IEEE J. Solid-State Circuits, vol.49, no.3, pp.695-707, March 2014.","DOI":"10.1109\/JSSC.2014.2304364"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] A. Donida, R. Cellier, A. Nagari, P. Malcovati, and A. Baschirotto, \u201cA 40-nm CMOS, 1.1-V, 101-dB dynamic-range, 1.7-mW continuous-time \u03a3 \u0394 ADC for a digital closed-loop Class-D amplifier,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers, vol.62, no.3, pp.645-653, March 2015.","DOI":"10.1109\/TCSI.2014.2373971"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] S. Weaver, B. Hershberg, and U.K. Moon, \u201cDigitally synthesized stochastic flash ADC using only standard digital cells,\u201d IEEE Trans. Circuits Syst. I: Reg. Papers, vol.61, no.1, pp.84-91, Jan. 2014.","DOI":"10.1109\/TCSI.2013.2268571"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] A. Ismail and M. Elmasry, \u201cA 6-bit 1.6-GS\/s low-power wideband flash ADC converter in 0.13-\u00b5m CMOS technology,\u201d IEEE J. Solid-State Circuits, vol.43, no.9, pp.1982-1990, Sept. 2008.","DOI":"10.1109\/JSSC.2008.2001936"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] A. Varzaghani, A. Kasapi, D. Loizos, S.H. Paik, S. Verma, S. Zogopoulos, and S. Sidiropoulos, \u201cA 10.3-GS\/s, 6-bit flash ADC for 10G ethernet applications,\u201d IEEE J. Solid-State Circuits, vol.48, no.12, pp.3038-3048, Dec. 2013.","DOI":"10.1109\/JSSC.2013.2279419"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Kuramochi, M. Kawabata, K. Uekusa, and A. Matsuzawa, \u201cA self-calibration technique for capacitor mismatch errors of an interleaved SAR ADC,\u201d IEICE Trans. Electronics, vol.E93-C, no.11, pp.1630-1637, Nov. 2010.","DOI":"10.1587\/transele.E93.C.1630"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] H. Wei, C.H. Chan, U.F. Chio, S.W. Sin, S.P. U, R. Martins, and F. Maloberti, \u201cAn 8-b 400-MS\/s 2-b-per-cycle SAR ADC with resistive DAC,\u201d IEEE J. Solid-State Circuits, vol.47, no.11, pp.2763-2772, Nov. 2012.","DOI":"10.1109\/JSSC.2012.2214181"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] L. Kull, T. Toifl, M. Schmatz, P. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. Andersen, and Y. Leblebici, \u201cA 90GS\/s 8b 667mW 64 \u00d7 interleaved SAR ADC in 32nm digital SOI CMOS,\u201d IEEE ISSCC Dig. Tech. Papers, pp.378-379, Feb. 2014.","DOI":"10.1109\/ISSCC.2014.6757477"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] S. Le Tual, P. Singh, C. Curis, and P. Dautriche, \u201cA 20GHz-BW 6b 10GS\/s 32mW time-interleaved SAR ADC with master T&H in 28nm UTBB FDSOI technology,\u201d IEEE ISSCC Dig. Tech. Papers, pp.382-383, Feb. 2014.","DOI":"10.1109\/ISSCC.2014.6757479"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and J. Craninckx, \u201cAn 820 \u00b5w 9b 40MS\/s noise-tolerant dynamic-SAR ADC in 90nm digital CMOS,\u201d IEEE ISSCC Dig. Tech. Papers, pp.238-610, Feb. 2008.","DOI":"10.1109\/ISSCC.2008.4523145"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] C.C. Liu, S.J. Chang, G.Y. Huang, Y.Z. Lin, C.M. Huang, C.H. Huang, L. Bu, and C.C. Tsai, \u201cA 10b 100MS\/s 1.13mW SAR ADC with binary-scaled error compensation,\u201d IEEE ISSCC Dig. Tech. Papers, pp.386-387, Feb. 2010.","DOI":"10.1109\/ISSCC.2010.5433970"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] M. Ranjbar, A. Mehrabi, and O. Oliaei, \u201cA low-power 1.92MHz CT delta sigma modulator with 5-bit successive approximation quantizer,\u201d IEEE Custom Integrated Circuits Conference, pp.5-8, Sept. 2009.","DOI":"10.1109\/CICC.2009.5280910"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] J. Fredenburg and M. Flynn, \u201cA 90-MS\/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC,\u201d IEEE J. Solid-State Circuits, vol.47, no.12, pp.2898-2904, Dec. 2012.","DOI":"10.1109\/JSSC.2012.2217874"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] C.H. Chen, Y. Zhang, J. Ceballos, and G. Temes, \u201cNoise-shaping SAR ADC using three capacitors,\u201d Electronics Letters, vol.49, no.3, pp.182-184, Jan. 2013.","DOI":"10.1049\/el.2012.4204"},{"key":"23","doi-asserted-by":"crossref","unstructured":"[23] H. Yoshizawa and G. Temes, \u201cSwitched-capacitor track-and-hold amplifiers with low sensitivity to op-amp imperfections,\u201d IEEE Trans. Circuits Syst. I: Reg. Papers, vol.54, no.1, pp.193-199, Jan. 2007.","DOI":"10.1109\/TCSI.2006.887454"},{"key":"24","doi-asserted-by":"crossref","unstructured":"[24] C. Wang, \u201cA 20-bit 25-kHz delta-sigma A\/D converter utilizing a frequency-shaped chopper stabilization scheme,\u201d IEEE J. Solid-State Circuits, vol.36, no.3, pp.566-569, March 2001.","DOI":"10.1109\/4.910497"},{"key":"25","doi-asserted-by":"crossref","unstructured":"[25] R. Walden, \u201cAnalog-to-digital converter survey and analysis,\u201d Selected Areas in Communications, IEEE Journal on, vol.17, no.4, pp.539-550, April 1999.","DOI":"10.1109\/49.761034"},{"key":"26","doi-asserted-by":"crossref","unstructured":"[26] R. Schreier and G.C. Temes, Understanding Delta-Sigma Data Converters, Wiley-IEEE Press, 2004.","DOI":"10.1109\/9780470546772"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] Z. Chen, M. Miyahara, and A. Matsuzawa, \u201cA 9.35-ENOB, 14.8 fJ\/conv.-step fully-passive noise-shaping SAR ADC,\u201d IEEE Symp. VLSI Circuits (VLSIC), pp.64-65, June 2015.","DOI":"10.1109\/VLSIC.2015.7231329"},{"key":"28","unstructured":"[28] B.E. Jonsson, \u201cUsing Figures-of-Merit to Evaluate Measured A\/D-Converter Performance,\u201d International Workshop on ADC Modeling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, pp.248-253, June 2011."}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E99.C\/6\/E99.C_623\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,9]],"date-time":"2019-09-09T02:53:02Z","timestamp":1567997582000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E99.C\/6\/E99.C_623\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":28,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2016]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e99.c.623","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016]]}}}