{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T20:40:25Z","timestamp":1742848825159,"version":"3.40.2"},"reference-count":26,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2012]]},"DOI":"10.1587\/transele.e95.c.534","type":"journal-article","created":{"date-parts":[[2012,4,2]],"date-time":"2012-04-02T04:19:57Z","timestamp":1333340397000},"page":"534-545","source":"Crossref","is-referenced-by-count":5,"title":["Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips"],"prefix":"10.1587","volume":"E95.C","author":[{"given":"Wei","family":"ZHONG","sequence":"first","affiliation":[{"name":"Graduate School of Information Production and Systems, Waseda University"}]},{"given":"Takeshi","family":"YOSHIMURA","sequence":"additional","affiliation":[{"name":"Graduate School of Information Production and Systems, Waseda University"}]},{"given":"Bei","family":"YU","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of Texas at Austin"}]},{"given":"Song","family":"CHEN","sequence":"additional","affiliation":[{"name":"Graduate School of Information Production and Systems, Waseda University"}]},{"given":"Sheqin","family":"DONG","sequence":"additional","affiliation":[{"name":"Department of Computer Science & Technology, Tsinghua University"}]},{"given":"Satoshi","family":"GOTO","sequence":"additional","affiliation":[{"name":"Graduate School of Information Production and Systems, Waseda University"}]}],"member":"532","reference":[{"doi-asserted-by":"crossref","unstructured":"[1] W. Zhong, B. Yu, S. Chen, T. Yoshimura, S. Dong, and S. Goto, “Application-specific network-on-chip synthesis: Cluster generation and network component insertion,” Proc. IEEE International Symposium on Quality Electronic Design, pp.1-6, 2011.","key":"1","DOI":"10.1109\/ISQED.2011.5770718"},{"doi-asserted-by":"crossref","unstructured":"[2] W.J. Dally and B. Towles, “Route packet, not wires: On-chip interconnection networks,” Proc. IEEE\/ACM Design Automation Conference, pp.684-689, 2001.","key":"2","DOI":"10.1145\/378239.379048"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/2.976921"},{"doi-asserted-by":"crossref","unstructured":"[4] J. Hu and R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” Proc. IEEE\/ACM Asia and South Pacific Design Automation Conference, pp.233-239, 2003.","key":"4","DOI":"10.1145\/1119772.1119818"},{"doi-asserted-by":"crossref","unstructured":"[5] S. Murali and G. De Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” Proc. IEEE Design Automation and Test in Europe Conference, vol.2, pp.896-901, 2004.","key":"5","DOI":"10.1109\/DATE.2004.1269002"},{"doi-asserted-by":"crossref","unstructured":"[6] M.B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, Lee Jae-Wook, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal, “The raw microprocessor: A computational fabric for software circuits and general-purpose programs,” Proc. IEEE Micro, pp.25-35, 2002.","key":"6","DOI":"10.1109\/MM.2002.997877"},{"doi-asserted-by":"crossref","unstructured":"[7] S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo, “Designing application-specific networks on chips with floorplan information,” Proc. IEEE\/ACM International Conference on Computer-Aided Design, pp.355-362, 2006.","key":"7","DOI":"10.1109\/ICCAD.2006.320058"},{"doi-asserted-by":"crossref","unstructured":"[8] S. Yan and B. Lin, “Application-specific network-on-chip architecture synthesis based on set partitions and steiner trees,” Proc. IEEE\/ACM Asia and South Pacific Design Automation Conference, pp.277-282, 2008.","key":"8","DOI":"10.1109\/ASPDAC.2008.4483955"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/TVLSI.2006.871762"},{"doi-asserted-by":"crossref","unstructured":"[10] S. Murali, C. Seiculescu, L. Benini, and G. De Micheli, “Synthesis of networks on chips for 3D systems on chips,” Proc. IEEE\/ACM Asia and South Pacific Design Automation Conference, pp.242-247, 2009.","key":"10","DOI":"10.1109\/ASPDAC.2009.4796487"},{"doi-asserted-by":"crossref","unstructured":"[11] D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini, and G. De Micheli, “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Trans. Parallel Distrib. Syst., vol.16, no.2, pp.113-129, 2005.","key":"11","DOI":"10.1109\/TPDS.2005.22"},{"doi-asserted-by":"crossref","unstructured":"[12] C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, “SunFloor 3D: A tool for networks on chip topology synthesis for 3D systems on chips,” Proc. IEEE Design Automation and Test in Europe Conference, pp.9-14, 2009.","key":"12","DOI":"10.1109\/DATE.2009.5090625"},{"doi-asserted-by":"crossref","unstructured":"[13] B. Yu, S. Dong, S. Chen, and S. Goto, “Floorplanning and topology generation for application-specific network-on-chip,” Proc. IEEE\/ACM Asia and South Pacific Design Automation Conference, pp.535-540, 2010.","key":"13","DOI":"10.1109\/ASPDAC.2010.5419825"},{"unstructured":"[14] X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. Cheng, and J. Gu, “Corner block list: An effective and efficient topological representation of non-slicing floorplan,” Proc. IEEE\/ACM International Conference on Computer-Aided Design, pp.8-12, 2000.","key":"14"},{"doi-asserted-by":"crossref","unstructured":"[15] A. Jalabert, S. Murali, L. Benini, and G. De Micheli, “×pipes Compiler: A tool for instantiating application specific networks-on-chip,” Proc. IEEE Design Automation and Test in Europe Conference, pp.884-889, 2004.","key":"15","DOI":"10.1109\/DATE.2004.1268999"},{"unstructured":"[16] OCP, http:\/\/www.ocpip.org","key":"16"},{"unstructured":"[17] S. Murali, Methodologies for reliable and efficient design of networks on chips, Ph.D. Thesis, Stanford University, March 2007.","key":"17"},{"doi-asserted-by":"crossref","unstructured":"[18] A. Pinto, L.P. Carloni, and A.L. Sangiovanni-Vincentelli, “Efficient Synthesis of Networks on Chip,” Proc. IEEE International Conference on Computer Design, pp.146-150, 2003.","key":"18","DOI":"10.1109\/ICCD.2003.1240887"},{"doi-asserted-by":"publisher","key":"19","DOI":"10.1109\/TCAD.2008.917968"},{"unstructured":"[20] Cbc, “ILP solver,” http:\/\/projects.coin-or.org\/Cbc","key":"20"},{"unstructured":"[21] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, WH Freeman and Company, San Francisco, 1979.","key":"21"},{"unstructured":"[22] R.K. Ahuja, T.L. Magnanti, and J.B. Orlin, Network Flows: Theory, Algorithms, and Applications, Prentice Hall\/Pearson, 2005.","key":"22"},{"doi-asserted-by":"crossref","unstructured":"[23] K. Goossens, A. Radulescu, and A. Hansson, “A unified approach to constrained mapping and routing on network-on-chip architectures,” Proc. IEEE\/ACM International Conference on Hardware\/Software Codesign and System Synthesis, pp.75-80, 2005.","key":"23","DOI":"10.1145\/1084834.1084857"},{"doi-asserted-by":"crossref","unstructured":"[24] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel hypergraph partitioning: Application in VLSI domain,” Proc. IEEE\/ACM Design Automation Conference, pp.526-529, 1997.","key":"24","DOI":"10.1145\/266021.266273"},{"unstructured":"[25] H. Wang, X. Zhu, L. Peh, and S. Malik, “Orion: A power-performance simulator for interconnection networks,” Proc. IEEE\/ACM International Symposium on Microarchitecture, pp.294-305, 2002.","key":"25"},{"unstructured":"[26] C. Zhuang, K. Sakanushi, L. Jin, and Y. Kajitani, “An enhanced Q-sequence augmented with empty-room-insertion and parenthesis trees,” Proc. IEEE Design Automation and Test in Europe Conference, pp.61-68, 2002.","key":"26"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E95.C\/4\/E95.C_4_534\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T20:08:32Z","timestamp":1742846912000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E95.C\/4\/E95.C_4_534\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"references-count":26,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2012]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e95.c.534","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"type":"print","value":"0916-8524"},{"type":"electronic","value":"1745-1353"}],"subject":[],"published":{"date-parts":[[2012]]}}}