{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T02:15:37Z","timestamp":1717208137728},"reference-count":18,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2012]]},"DOI":"10.1587\/transele.e95.c.414","type":"journal-article","created":{"date-parts":[[2012,4,2]],"date-time":"2012-04-02T04:19:57Z","timestamp":1333340397000},"page":"414-420","source":"Crossref","is-referenced-by-count":9,"title":["Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices"],"prefix":"10.1587","volume":"E95.C","author":[{"given":"Kiyoshi","family":"TAKEUCHI","sequence":"first","affiliation":[{"name":"Renesas Electronics Corp."}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki, “Managing process variation in Intel's 45nm CMOS technology,” Intel Technology Journal, vol.12, pp.93-109, 2008."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] K. Takeuchi, A. Nishida, and T. Hiramoto, “Random fluctuations in scaled MOS devices,” Proc. SISPAD, pp.79-85, 2009.","DOI":"10.1109\/SISPAD.2009.5290243"},{"key":"3","unstructured":"[3] H.-S. Wong and Y. Taur, “Three-dimensional “atomistic” simulation of discrete random dopant distribution effects in sub-0.1µm MOSFET's,” IEDM Tech. Dig., pp.705-708, 1993."},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/16.333844"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/16.735728"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] K. Takeuchi, T. Fukai, T. Tsunomura, A.T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, “Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies,” IEDM Tech. Dig., pp.467-470, 2007.","DOI":"10.1109\/IEDM.2007.4418975"},{"key":"7","unstructured":"[7] K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai, and Y. Hayashi, “Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude,” Dig. Symp. VLSI Tech., pp.54-55, 2009."},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.910605"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] T. Grasser, B. Kaczer, W. Goes, H. Reisinger, Th. Aichinger, Ph. Hehenberger, P.-J. Wagner, F. Schanovsky, J. Franco, Ph. Roussel, and M. Nelhiebel, “Recent advances in understanding the bias temperature instability,” IEDM Tech. Dig., pp.82-85, 2010.","DOI":"10.1109\/IEDM.2010.5703295"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, and L. Camus, “NBTI degradation: From transistor to SRAM arrays,” Proc. IRPS, pp.289-300, 2008.","DOI":"10.1109\/RELPHY.2008.4558900"},{"key":"11","unstructured":"[11] K. Takeuchi, T. Tatsumi, and A. Furukawa, “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation,” IEDM Tech. Dig., pp.841-844, 1997."},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/16.711362"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2090159"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1080\/00018738900101122"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026390"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] K. Takeuchi, T. Nagumo, K. Takeda, S. Asayama, S. Yokogawa, K. Imai, and Y. Hayashi, “Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment,” Dig. Symp. VLSI Tech., pp.189-190, 2010.","DOI":"10.1109\/VLSIT.2010.5556222"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] T. Nagumo, K. Takeuchi, S. Yokogawa, K. Imai, and Y. Hayashi, “New analysis methods for comprehensive understanding of random telegraph noise,” IEDM Tech. Dig., pp.759-762, 2009.","DOI":"10.1109\/IEDM.2009.5424230"},{"key":"18","unstructured":"[18] K. Takeuchi, T. Nagumo, and T. Hase, “Comprehensive SRAM design methodology for RTN reliability,” Dig. Symp. VLSI Tech., pp.130-131, 2011."}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E95.C\/4\/E95.C_4_414\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,26]],"date-time":"2021-04-26T05:18:21Z","timestamp":1619414301000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/transele\/E95.C\/4\/E95.C_4_414\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2012]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e95.c.414","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012]]}}}