{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,5]],"date-time":"2024-07-05T09:17:02Z","timestamp":1720171022825},"reference-count":26,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2011]]},"DOI":"10.1587\/transele.e94.c.1120","type":"journal-article","created":{"date-parts":[[2011,6,3]],"date-time":"2011-06-03T14:53:39Z","timestamp":1307112819000},"page":"1120-1126","source":"Crossref","is-referenced-by-count":1,"title":["Analytical Drain Current Modeling of Dual-Material Surrounding-Gate MOSFETs"],"prefix":"10.1587","volume":"E94-C","author":[{"given":"Zunchao","family":"LI","sequence":"first","affiliation":[{"name":"Department of Microelectronics, Xi'an Jiaotong University"}]},{"given":"Jinpeng","family":"XU","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, Xi'an Jiaotong University"}]},{"given":"Linlin","family":"LIU","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, Xi'an Jiaotong University"}]},{"given":"Feng","family":"LIANG","sequence":"additional","affiliation":[{"name":"Department of Microelectronics, Xi'an Jiaotong University"}]},{"given":"Kuizhi","family":"MEI","sequence":"additional","affiliation":[{"name":"Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University"}]}],"member":"532","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/16.249482"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/16.469401"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] J.T. Park, J.P. Colinge, and C.H. Diaze, “Pi-gate SOI MOSFET's,” IEEE Electron Device Lett., vol.22, no.8, pp.405-406, Aug. 2001.","DOI":"10.1109\/55.936358"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/16.75168"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] Z.C. Li, R.Z. Zhang, F. Liang, and Z.Y. Yang, “Analytical and numerical study of the impact of halos on surrounding-gate MOSFETs,” IEICE Trans. Electron., vol.E92-C, no.4, pp.558-563, April 2009.","DOI":"10.1587\/transele.E92.C.558"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.890264"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] L. Risch, “Pushing CMOS beyond the roadmap,” Solid State Electron., vol.50, no.4, pp.527-535, April 2006.","DOI":"10.1016\/j.sse.2006.03.026"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/16.974754"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.843969"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/16.954477"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.880371"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.823803"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.841276"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.833961"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] V. Misra, H. Zong, and H. Lazar, “Electrical properties of Ru-based alloy gate electrodes for dual gate Si-CMOS,” IEEE Electron Device Lett., vol.23, no.6, pp.354-356, June 2002.","DOI":"10.1109\/LED.2002.1004233"},{"key":"16","unstructured":"[16] Synopsys, SenTaurus Device User Guide, Synopsys Inc., 2006."},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] A. Kranti, S. Haldar, and R.S. Gupta, “Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical\/surrounding gate MOSFET,” Microelectron. Eng., vol.56, no.3, pp.241-259, Aug. 2001.","DOI":"10.1016\/S0167-9317(00)00419-6"},{"key":"18","unstructured":"[18] T. Endoh, T. Nakamura, and F. Masuoka, “An accurate model of fully-depleted surrounding gate transistor (FD-SGT),” IEICE Trans. Electron., vol.E80-C, no.7, pp.905-910, July 1997."},{"key":"19","unstructured":"[19] T. Endoh, T. Nakamura, and F. Masuoka, “An analytic steady-state current-voltage characteristics of short channel fully-depleted surrounding gate transistor (FD-SGT),” IEICE Trans. Electron., vol.E80-C, no.7, pp.911-917, July 1997."},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2007.01.003"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, G. Pananakakis, and R. Clerc, “A compact drain current model of short channel cylindrical gate-all-around MOSFETs,” Semicond. Sci. Technol., vol.24, no.7, 075017, July 2009.","DOI":"10.1088\/0268-1242\/24\/7\/075017"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1983.21185"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1979.19547"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(02)00268-X"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/16.293312"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(95)00083-6"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transele\/E94.C\/6\/E94.C_6_1120\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,26]],"date-time":"2021-04-26T05:09:43Z","timestamp":1619413783000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transele\/E94.C\/6\/E94.C_6_1120\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"references-count":26,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2011]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e94.c.1120","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011]]}}}