{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T10:35:33Z","timestamp":1648895733402},"reference-count":6,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Electron."],"published-print":{"date-parts":[[2009]]},"DOI":"10.1587\/transele.e92.c.281","type":"journal-article","created":{"date-parts":[[2009,3,19]],"date-time":"2009-03-19T06:05:00Z","timestamp":1237442700000},"page":"281-285","source":"Crossref","is-referenced-by-count":1,"title":["An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability"],"prefix":"10.1587","volume":"E92-C","author":[{"given":"Koichi","family":"HAMAMOTO","sequence":"first","affiliation":[{"name":"Department of Information Systems Engineering, Osaka University"}]},{"given":"Hiroshi","family":"FUKETA","sequence":"additional","affiliation":[{"name":"Department of Information Systems Engineering, Osaka University"}]},{"given":"Masanori","family":"HASHIMOTO","sequence":"additional","affiliation":[{"name":"Department of Information Systems Engineering, Osaka University"},{"name":"JST CREST"}]},{"given":"Yukio","family":"MITSUYAMA","sequence":"additional","affiliation":[{"name":"Department of Information Systems Engineering, Osaka University"},{"name":"JST CREST"}]},{"given":"Takao","family":"ONOYE","sequence":"additional","affiliation":[{"name":"Department of Information Systems Engineering, Osaka University"},{"name":"JST CREST"}]}],"member":"532","reference":[{"key":"1","unstructured":"[1] J.W. Tschanz, J.T. Kao, S.G. Narendra, R. Nair, D.A. Antoniadis, A.P. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, ” IEEE JSSC, vol.37, no.11, pp.1396-1402, Nov. 2002."},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] S. Narendra, A. Keshavarzi, B.A. Bloechel, S. Borkar, and V. De, “Forward body bias for microprocessors in 130-nm technology generation and beyond, ” IEEE JSSC, vol.38, no.5, pp.696-701, May 2003.","DOI":"10.1109\/JSSC.2003.810054"},{"key":"3","unstructured":"[3] S.G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies, Springer, 2006."},{"key":"4","unstructured":"[4] K. Furusawa, Analysis and Application of Body Bias Controlled CMOS Circuits, Master Dissertation, Kyoto University, 2005."},{"key":"5","unstructured":"[5] S. Henzler, Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies, pp.52-55, Springer, 2007."},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] K. Nose, M. Hirabayashi, H. Kawaguchi, and T. Sakurai, “VTH<\/sub>-hopping scheme to reduce subthreshold leakage for low-power processors, ” IEEE JSSC, vol.37, no.3, pp.413-419, March 2002.","DOI":"10.1109\/4.987094"}],"container-title":["IEICE Transactions on Electronics"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transele\/E92.C\/2\/E92.C_2_281\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,26]],"date-time":"2021-04-26T05:03:46Z","timestamp":1619413426000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transele\/E92.C\/2\/E92.C_2_281\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"references-count":6,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2009]]}},"URL":"https:\/\/doi.org\/10.1587\/transele.e92.c.281","relation":{},"ISSN":["0916-8524","1745-1353"],"issn-type":[{"value":"0916-8524","type":"print"},{"value":"1745-1353","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009]]}}}