乐胖代购免代理版

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Gonzalez, et al.<\/i>: \u201cThe 24-core POWER9 processor with adaptive clocking, 25-Gb\/s accelerator links, and 16-Gb\/s PCIe Gen4,\u201d IEEE J. Solid-State Circuits 53<\/b> (2018) 91 (DOI: 10.1109\/JSSC.2017.2748623).","DOI":"10.1109\/JSSC.2017.2748623"},{"key":"2","doi-asserted-by":"crossref","unstructured":"[2] C. Schaef, et al.<\/i>: \u201cA light-load efficient fully integrated voltage regulator in 14-nm CMOS with 2.5-nH package-embedded air-core inductors,\u201d IEEE J. Solid-State Circuits 54<\/b> (2019) 3316 (DOI: 10.1109\/JSSC.2019.2946218).","DOI":"10.1109\/JSSC.2019.2946218"},{"key":"3","doi-asserted-by":"crossref","unstructured":"[3] G.W. Roberts and M. Ali-Bakhshian: \u201cA brief introduction to time-to-digital and digital-to-time converters,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs 57<\/b> (2010) 153 (DOI: 10.1109\/TCSII.2010.2043382).","DOI":"10.1109\/TCSII.2010.2043382"},{"key":"4","doi-asserted-by":"crossref","unstructured":"[4] S. Zhu, et al.<\/i>: \u201cA skew-free 10GS\/s 6bit CMOS ADC with compact time-domain signal folding and inherent DEM,\u201d IEEE J. Solid-State Circuits 51<\/b> (2016) 1785 (DOI: 10.1109\/JSSC.2016.2558487).","DOI":"10.1109\/JSSC.2016.2558487"},{"key":"5","doi-asserted-by":"crossref","unstructured":"[5] S. Zhu, et al.<\/i>: \u201cA 0.073-mm^{2<\/sup> 10-GS\/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM,\u201d CICC (2015) 1 (DOI: 10.1109\/CICC.2015.7338384).","DOI":"10.1109\/CICC.2015.7338384"},{"key":"6","doi-asserted-by":"crossref","unstructured":"[6] L.-J. Chen and S.-I. Liu: \u201cA 10-bit 40-MS\/s time-domain two-step ADC with short calibration time,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs 63<\/b> (2016) 126 (DOI: 10.1109\/TCSII.2015.2483360).","DOI":"10.1109\/TCSII.2015.2483360"},{"key":"7","doi-asserted-by":"crossref","unstructured":"[7] K.-J. Moon, et al.<\/i>: \u201cA 28-nm CMOS 12-bit 250-MS\/s voltage-current-time domain 3-stage pipelined ADC,\u201d IEEE Trans. Circuits Syst. II, Exp. Briefs 67<\/b> (2020) 2843 (DOI: 10.1109\/TCSII.2020.2990910).","DOI":"10.1109\/TCSII.2020.2990910"},{"key":"8","doi-asserted-by":"crossref","unstructured":"[8] I.-M. Yi, et al.<\/i>: \u201cA 4-GS\/s 11.3-mW 7-bit time-based ADC with folding voltage-to-time converter and pipelined TDC in 65-nm CMOS,\u201d IEEE J. Solid-State Circuits 56<\/b> (2021) 465 (DOI: 10.1109\/JSSC.2020.3025605).","DOI":"10.1109\/JSSC.2020.3025605"},{"key":"9","doi-asserted-by":"crossref","unstructured":"[9] M. Zhang, et al.<\/i>: \u201cAn 8-bit 10-GS\/s 16 \u00d7 interpolation-based time-domain ADC with <1.5-ps uncalibrated quantization steps,\u201d IEEE J. Solid-State Circuits 56<\/b> (2020) 3225 (DOI: 10.1109\/JSSC.2020.3012776).","DOI":"10.1109\/JSSC.2020.3012776"},{"key":"10","doi-asserted-by":"crossref","unstructured":"[10] B. Xu, et al.<\/i>: \u201cA 23-mW 24-GS\/s 6-bit voltage-time hybrid time-interleaved ADC in 28-nm CMOS,\u201d IEEE J. Solid-State Circuits 52<\/b> (2017) 1091 (DOI: 10.1109\/JSSC.2016.2642204).","DOI":"10.1109\/JSSC.2016.2642204"},{"key":"11","doi-asserted-by":"crossref","unstructured":"[11] A. Esmailiyan, et al.<\/i>: \u201cA 0.36-V 5-MS\/s time-mode flash ADC with dickson-charge-pump-based comparators in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers 67<\/b> (2020) 1789 (DOI: 10.1109\/TCSI.2020.2969804).","DOI":"10.1109\/TCSI.2020.2969804"},{"key":"12","doi-asserted-by":"crossref","unstructured":"[12] S. Zhu, et al.<\/i>: \u201cA 2-GS\/s 8-bit non-interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS,\u201d IEEE J. Solid-State Circuits 53<\/b> (2018) 1172 (DOI: 10.1109\/JSSC.2017.2774280).","DOI":"10.1109\/JSSC.2017.2774280"},{"key":"13","doi-asserted-by":"crossref","unstructured":"[13] I.-M. Yi, et al.<\/i>: \u201cA 15.1-mW 6-GS\/s 6-bit single-channel flash ADC with selectively activated 8 \u00d7 time-domain latch interpolation,\u201d IEEE J. Solid-State Circuits 56<\/b> (2021) 455 (DOI: 10.1109\/JSSC.2020.3017229).","DOI":"10.1109\/JSSC.2020.3017229"},{"key":"14","doi-asserted-by":"crossref","unstructured":"[14] Y. Lyu and F. Tavernier: \u201cA 4-GS\/s 39.9-dB SNDR 11.7-mW hybrid voltage-time two-step ADC with feedforward ring oscillator-based TDCs,\u201d IEEE J. Solid-State Circuits 55<\/b> (2020) 1807 (DOI: 10.1109\/JSSC.2020.2987699).","DOI":"10.1109\/JSSC.2020.2987699"},{"key":"15","doi-asserted-by":"crossref","unstructured":"[15] K. Ohhata, et al.<\/i>: \u201cA 2.3-mW, 1-GHz, 8-bit fully time-based two-step ADC using a high-linearity dynamic VTC,\u201d IEEE J. Solid-State Circuits 54<\/b> (2019) 2038 (DOI: 10.1109\/JSSC.2019.2907401).","DOI":"10.1109\/JSSC.2019.2907401"},{"key":"16","doi-asserted-by":"crossref","unstructured":"[16] J. Muhlestein, et al.<\/i>: \u201cA 73dB SNDR 20MS\/s 1.28mW SAR-TDC using hybrid two-step quantization,\u201d CICC (2017) 1 (DOI: 10.1109\/CICC.2017.7993701).","DOI":"10.1109\/CICC.2017.7993701"},{"key":"17","doi-asserted-by":"crossref","unstructured":"[17] M. Liu, et al.<\/i>: \u201cA 10-bit 2.5-GS\/s two-step ADC with selective time-domain quantization in 28-nm CMOS,\u201d IEEE Trans. Circuits Syst. I, Reg. Papers 69<\/b> (2021) 1091 (DOI: 10.1109\/TCSI.2021.3129192).","DOI":"10.1109\/TCSI.2021.3129192"},{"key":"18","doi-asserted-by":"crossref","unstructured":"[18] H. Tai, et al.<\/i>: \u201cA 0.85fJ\/conversion-step 10b 200kS\/s subranging SAR ADC in 40nm CMOS,\u201d ISSCC (2014) 196 (DOI: 10.1109\/ISSCC.2014.6757397).","DOI":"10.1109\/ISSCC.2014.6757397"},{"key":"19","doi-asserted-by":"crossref","unstructured":"[19] J.-H. Tsai, et al.<\/i>: \u201cA 0.003mm^{2<\/sup> 10b 240MS\/s 0.7mW SAR ADC in 28nm CMOS with digital error correction and correlated-reversed switching,\u201d IEEE J. Solid-State Circuits 50<\/b> (2015) 1382 (DOI: 10.1109\/JSSC.2015.2413850).","DOI":"10.1109\/JSSC.2015.2413850"},{"key":"20","doi-asserted-by":"crossref","unstructured":"[20] C. Liu, et al.<\/i>: \u201cA 10bit 320MS\/s low-cost SAR ADC for IEEE 802.11ac applications in 20nm CMOS,\u201d IEEE J. Solid-State Circuits 50<\/b> (2015) 2645 (DOI: 10.1109\/JSSC.2015.2466475).","DOI":"10.1109\/JSSC.2015.2466475"},{"key":"21","doi-asserted-by":"crossref","unstructured":"[21] Y.M. Tousi and E. Afshari: \u201cA miniature 2mW 4bit 1.2GS\/s delay-line-based ADC in 65nm CMOS,\u201d IEEE J. Solid-State Circuits 46<\/b> (2011) 2312 (DOI: 10.1109\/JSSC.2011.2162186).","DOI":"10.1109\/JSSC.2011.2162186"},{"key":"22","doi-asserted-by":"crossref","unstructured":"[22] Y. Xu, et al.<\/i>: \u201c5-bit 5-GS\/s noninterleaved time-based ADC in 65-nm CMOS for radio-astronomy applications,\u201d IEEE Trans. Very Large Scale Integr. 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Su, et al.<\/i>: \u201cA 280MS\/s 12b SAR-assisted hybrid ADC with time domain sub-range quantizer in 45nm CMOS,\u201d CICC (2019) 1 (DOI: 10.1109\/CICC.2019.8780209).","DOI":"10.1109\/CICC.2019.8780209"},{"key":"27","doi-asserted-by":"crossref","unstructured":"[27] K. Ohhata, et al.<\/i>: \u201cA 900-MHz, 3.5-mW, 8-bit pipelined subranging ADC combining flash ADC and TDC,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26<\/b> (2018) 1777 (DOI: 10.1109\/TVLSI.2018.2827943).","DOI":"10.1109\/TVLSI.2018.2827943"},{"key":"28","doi-asserted-by":"crossref","unstructured":"[28] W. El-Halwagy, et al.<\/i>: \u201cA 100-MS\/s-5-GS\/s, 13-5-bit nyquist-rate reconfigurable time-domain ADC,\u201d IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26<\/b> (2018) 1967 (DOI: 10.1109\/TVLSI.2018.2850806).","DOI":"10.1109\/TVLSI.2018.2850806"},{"key":"29","doi-asserted-by":"crossref","unstructured":"[29] V. Dhanasekaran, et al.<\/i>: \u201cA continuous time multi-bit \u0394\u03a3 ADC using time domain quantizer and feedback element,\u201d IEEE J. Solid-State Circuits 46<\/b> (2011) 639 (DOI: 10.1109\/JSSC.2010.2099893).","DOI":"10.1109\/JSSC.2010.2099893"},{"key":"30","doi-asserted-by":"crossref","unstructured":"[30] L. Du, et al.<\/i>: \u201cA 10-bit 100MS\/s subrange SAR ADC with time-domain quantization,\u201d ISCAS (2014) 301 (DOI: 10.1109\/ISCAS.2014.6865125).","DOI":"10.1109\/ISCAS.2014.6865125"}],"container-title":["IEICE Electronics Express"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/7\/19_19.20220074\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,16]],"date-time":"2022-04-16T04:39:17Z","timestamp":1650083957000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.jstage.jst.go.jp\/article\/elex\/19\/7\/19_19.20220074\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,10]]},"references-count":30,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2022]]}},"URL":"https:\/\/doi.org\/10.1587\/elex.19.20220074","relation":{},"ISSN":["1349-2543"],"issn-type":[{"value":"1349-2543","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4,10]]},"article-number":"19.20220074"}}}}