乐胖代购免代理版

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Shi, et al.<\/i>: \u201cA low-jitter and low-power CMOS PLL for clock multiplication,\u201d Proc. 32nd European Solid-State Circuits Conference (2006) 174 (DOI: 10.1109\/ESSCIR.2006.307559)."},{"key":"2","unstructured":"[2] J. Kim, et al.<\/i>: \u201cA 16-to-40 Gb\/s quarter-rate NRZ\/PAM4 dual-mode transmitter in 14 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 1 (DOI: 10.1109\/ISSCC.2015.7062925)."},{"key":"3","unstructured":"[3] G. Shu, et al.<\/i>: \u201cA 4-to-10.5 Gb\/s continuous-rate digital clock and data recovery with automatic frequency acquisition,\u201d IEEE J. Solid-State Circuits 51<\/b> (2016) 428 (DOI: 10.1109\/JSSC.2015.2497963)."},{"key":"4","doi-asserted-by":"publisher","unstructured":"[4] R. B. Staszewski, et al.<\/i>: \u201cAll-digital PLL and transmitter for mobile phones,\u201d IEEE J. Solid-State Circuits 40<\/b> (2005) 2469 (DOI: 10.1109\/JSSC.2005.857417).","DOI":"10.1109\/JSSC.2005.857417"},{"key":"5","unstructured":"[5] Y. W. Li, et al.<\/i>: \u201cA reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22 nm high-k tri-gate LP CMOS,\u201d ISSCC Dig. Tech. Papers (2012) 70 (DOI: 10.1109\/ISSCC.2012.6176934)."},{"key":"6","unstructured":"[6] D. M. Fischette, et al.<\/i>: \u201cA 45 nm SOI-CMOS dual-PLL processor clock system for multi-protocol I\/O,\u201d ISSCC Dig. Tech. Papers (2010) 246 (DOI: 10.1109\/ISSCC.2010.5433942)."},{"key":"7","unstructured":"[7] T. Kawamoto, et al.<\/i>: \u201cMulti-standard 185 fsrms 0.3-to-28 Gb\/s 40 dB backplane signal conditioner with adaptive pattern-match 36-tap DFE and data-rate-adjustment PLL in 28 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2015) 1 (DOI: 10.1109\/ISSCC.2015.7062922)."},{"key":"8","doi-asserted-by":"publisher","unstructured":"[8] J. Zhu, et al.<\/i>: \u201cA 0.0021 mm^{2<\/sup> 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS,\u201d IEEE J. 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Liao, et al.<\/i>: \u201cA low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator,\u201d Proc. IEEE Radio Freq. Integr. Circuits Symp. (2017) 108 (DOI: 10.1109\/RFIC.2017.7969029)."},{"key":"13","unstructured":"[13] C.-F. Liang and K.-J. Hsiao: \u201cAn injection-locked ring PLL with self-aligned injection window,\u201d ISSCC Dig. Tech. Papers (2011) 90 (DOI: 10.1109\/ISSCC.2011.5746232)."},{"key":"14","unstructured":"[14] P. Park, et al.<\/i>: \u201cAn all-digital clock generator using a fractionally injection-locked oscillator in 65 nm CMOS,\u201d ISSCC Dig. Tech. Papers (2012) 336 (DOI: 10.1109\/ISSCC.2012.6177036)."},{"key":"15","doi-asserted-by":"publisher","unstructured":"[15] A. Li, et al.<\/i>: \u201cA spur-and-phase noise-filtering technique for inductor-less fractional-N injection-locked PLLs,\u201d IEEE J. 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Sun, et al.<\/i>: \u201cA 1.75 mW 1.1 GHz semi-digital fractional-N PLL with TDC-less hybrid loop control,\u201d IEEE Microw. Wireless Compon. Lett. 22<\/b> (2012) 654 (DOI: 10.1109\/LMWC.2012.2228178).","DOI":"10.1109\/LMWC.2012.2228178"},{"key":"20","unstructured":"[20] R. He, et al.<\/i>: \u201cA low-cost, leakage-insensitive semi-digital PLL with linear phase detection and FIR-embedded digital frequency acquisition,\u201d Proc. IEEE A-SSCC (2010) 197 (DOI: 10.1109\/ASSCC.2010.5716589)."},{"key":"21","doi-asserted-by":"publisher","unstructured":"[21] A. Elkholy, et al.<\/i>: \u201cA 2.0\u20135.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,\u201d IEEE J. Solid-State Circuits 51<\/b> (2016) 1771 (DOI: 10.1109\/JSSC.2016.2557807).","DOI":"10.1109\/JSSC.2016.2557807"},{"key":"22","doi-asserted-by":"publisher","unstructured":"[22] M. S.-W. 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