{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T02:12:59Z","timestamp":1648779179070},"reference-count":37,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2010,2,24]],"date-time":"2010-02-24T00:00:00Z","timestamp":1266969600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["ECS-0319002","CCF-0311500"],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2010,2,24]]},"abstract":"Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.<\/jats:p>","DOI":"10.1155\/2010\/251210","type":"journal-article","created":{"date-parts":[[2010,2,24]],"date-time":"2010-02-24T15:31:39Z","timestamp":1267025499000},"page":"1-25","source":"Crossref","is-referenced-by-count":11,"title":["Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments"],"prefix":"10.1155","volume":"2010","author":[{"given":"Saumil G.","family":"Merchant","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, George Washington University, 20101 Academic Way, Ashburn, VA 20147-2604, USA"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-0875-5278","authenticated-orcid":true,"given":"Gregory D.","family":"Peterson","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of Tennessee, 414 Ferris Hall, Knoxville, TN 37996-2100, USA"}]}],"member":"98","reference":[{"key":"3","volume-title":"Overview of neural hardware","year":"1995"},{"key":"7","volume-title":"Digital systems for neural networks","volume":"57","year":"1995"},{"issue":"1","key":"8","first-page":"11","volume":"6","year":"1996","journal-title":"Neural Network World"},{"issue":"8","key":"9","doi-asserted-by":"crossref","first-page":"847","DOI":"10.1109\/12.707586","volume":"47","year":"1998","journal-title":"IEEE Transactions on Computers"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.819420"},{"key":"17","volume-title":"On the arithmetic precision for implementing back-propagation networks on FPGA: a case study","year":"2006"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/12.210171"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2006.875980"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2004.825221"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/72.182695"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1049\/el:19940223"},{"issue":"3","key":"38","doi-asserted-by":"crossref","first-page":"688","DOI":"10.1109\/4.307","volume":"23","year":"1988","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"42","volume-title":"Neural network implementation using reconfigurable architectures","year":"1994"},{"key":"50","doi-asserted-by":"publisher","DOI":"10.1109\/4.121550"},{"key":"56","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.835665"},{"key":"59","volume-title":"Back-propagation algorithm achieving 5 Gops on the Virtex-E","year":"2006"},{"issue":"6","key":"61","doi-asserted-by":"crossref","first-page":"628","DOI":"10.1109\/12.773799","volume":"48","year":"1999","journal-title":"IEEE Transactions on Computers"},{"key":"65","doi-asserted-by":"publisher","DOI":"10.1109\/72.217187"},{"key":"69","volume-title":"FPNA: applications and implementations","year":"2006"},{"key":"70","volume-title":"FPNA: concepts and properties","year":"2006"},{"key":"71","volume-title":"An electrically trainable artificial neural network (ETANN) with 10240 \u2018floating gate\u2019 synapses","year":"1990"},{"key":"72","doi-asserted-by":"publisher","DOI":"10.1109\/72.129415"},{"key":"73","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36553-2_25"},{"key":"74","volume-title":"FPGA neurocomputers","year":"2006"},{"issue":"23","key":"75","doi-asserted-by":"crossref","first-page":"5077","DOI":"10.1364\/AO.26.005077","volume":"26","year":"1987","journal-title":"Applied Optics"},{"key":"76","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.842871"},{"key":"77","doi-asserted-by":"publisher","DOI":"10.1109\/4.133157"},{"key":"81","doi-asserted-by":"publisher","DOI":"10.1109\/31.55034"},{"issue":"12","key":"82","first-page":"34","volume":"5","year":"1990","journal-title":"AI Expert"},{"key":"84","doi-asserted-by":"publisher","DOI":"10.1109\/72.129408"},{"key":"86","doi-asserted-by":"publisher","DOI":"10.1109\/72.129409"},{"key":"87","doi-asserted-by":"publisher","DOI":"10.1109\/72.129422"},{"key":"88","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2006.877535"},{"key":"90","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19941103"},{"key":"91","doi-asserted-by":"publisher","DOI":"10.1109\/72.914525"},{"key":"94","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2007.900239"},{"key":"100","doi-asserted-by":"crossref","first-page":"179","DOI":"10.1111\/j.1469-1809.1936.tb02137.x","volume":"7","year":"1936","journal-title":"Annals of Eugenics"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2010\/251210.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2010\/251210.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2010\/251210.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T04:08:44Z","timestamp":1607486924000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2010\/251210\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2,24]]},"references-count":37,"alternative-id":["251210","251210"],"URL":"https:\/\/doi.org\/10.1155\/2010\/251210","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2,24]]}}}