{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T10:40:36Z","timestamp":1723113636178},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"A central problem in building large scale parallel machines is the design of the interconnection network. Interconnection\nnetwork design is largely constrained by packaging technology. We start with a generic set of packaging\nrestrictions and evaluate different network organizations under a random traffic model. Our results indicate that\ncustomizing the network topology to the packaging constraints is useful. Some of the general principles that arise\nout of this study are: 1) Making the networks denser at the lower levels of the packaging hierarchy has a significant\npositive impact on global communication performance, 2) It is better to organize a fixed amount of communication\nbandwidth as a smaller number of high bandwidth channels, 3) Providing the processors with the ability to tolerate\nlatencies (by using multithreading<\/jats:italic>) is very useful in improving performance.<\/jats:p>","DOI":"10.1155\/1995\/57617","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"375-388","source":"Crossref","is-referenced-by-count":0,"title":["Designing Interconnection Networks forMulti\u2010level Packaging"],"prefix":"10.1155","volume":"2","author":[{"given":"M. T.","family":"Raghunath","sequence":"first","affiliation":[]},{"given":"Abhiram","family":"Ranade","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/057617.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1995\/057617.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/57617","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T09:43:01Z","timestamp":1723110181000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/57617"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/57617"],"URL":"https:\/\/doi.org\/10.1155\/1995\/57617","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}