{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T10:40:36Z","timestamp":1723113636157},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":1826,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1995,1]]},"abstract":"It is well known that the hypercube has a rich set of good properties, and consequently it has been recognized an\nideal structure for parallel computation. Nevertheless, according to the current VLSI technology, the implementation\nfeasibility of the hypercube remains questionable when the size of the hypercube becomes large. Recent research\nefforts have been concentrated on finding good alternatives to the hypercube. The star graph was shown having\nmany desirable properties of the hypercube, and in several aspects, the star graph is better than the hypercube.\nHowever, we observe that the star graph as a network has several disadvantages, compared with the hypercube. In\nthis paper, we propose a class of new networks, the star\u2010hypercube hybrid networks (or the SH<\/jats:italic> networks). The SH<\/jats:italic>\nnetwork is a simple combination of both the star graph and the hypercube. This class of networks contains the\nstar graph and the hypercube as subclasses. We show that the SH<\/jats:italic> network is an efficient and versatile network for\nparallel computation, since it shares properties of both the hypercube and the star graph, and remedies several\nmajor disadvantages of the hypercube and the star graph. This class of networks provide more flexibility in choosing\nthe size, degree, number of vertices, degree of fault tolerance, etc. in designing massively parallel computing\nstructures feasible for VLSI implementations.<\/jats:p>","DOI":"10.1155\/1995\/10431","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"365-374","source":"Crossref","is-referenced-by-count":1,"title":["Trade\u2010Off Considerations in Designing Efficient VLSIFeasible Interconnection Networks"],"prefix":"10.1155","volume":"2","author":[{"given":"S. Q.","family":"Zheng","sequence":"first","affiliation":[]},{"given":"B.","family":"Cong","sequence":"additional","affiliation":[]},{"given":"S.","family":"Bettayeb","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1995,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1995\/010431.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1995\/10431","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T09:42:53Z","timestamp":1723110173000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1995\/10431"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1995,1]]}},"alternative-id":["10.1155\/1995\/10431"],"URL":"https:\/\/doi.org\/10.1155\/1995\/10431","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1995,1]]}}}