{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T05:10:02Z","timestamp":1723093802460},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2364,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware\nmodels written in VHDL. We survey central event queue, conservative distributed and optimistic distributed\nPDES algorithms, and discuss aspects of the semantics of VHDL and VHDL\u201092 that affect the use of these\nalgorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the\nUniversity of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We\npresent measurements taken from this kernel simulating some benchmark models. It appears that this technique,\nwhich is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop\nmultiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of\nuseful parallelism achievable on gate level models with this technique appears to be limited.<\/jats:p>","DOI":"10.1155\/1994\/86178","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"1-16","source":"Crossref","is-referenced-by-count":1,"title":["Execution of VHDL Models Using Parallel DiscreteEvent Simulation Algorithms"],"prefix":"10.1155","volume":"2","author":[{"given":"Peter J.","family":"Ashenden","sequence":"first","affiliation":[]},{"given":"Henry","family":"Detmold","sequence":"additional","affiliation":[]},{"given":"Wayne S.","family":"McKeen","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1993,7,12]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/086178.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/86178","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:44:20Z","timestamp":1723092260000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/86178"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1993,7,12]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/86178"],"URL":"https:\/\/doi.org\/10.1155\/1994\/86178","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1993,7,12]]}}}