{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:10:02Z","timestamp":1723090202855},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2191,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"In this paper, we address the technology mapping for RAM\u2010based FPGA. Functional decomposition is applied\nto decompose a large function into a set of smaller subfunctions such that each subfunction can be implemented\nusing a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically for\ntotally symmetric functions. A Fast-Decompose<\/jats:italic> algorithm based on weight dependency is proposed. The second\npart deals with general functions. We consider some techniques such as output partition, variable partition, don\u2032t\ncare assignment and encoding<\/jats:italic> to minimize the number of subfunctions derived. Using these techniques together,\nour tool, Fun-Map<\/jats:italic>, improves the mapping results compared with other tools in terms of area and delay.<\/jats:p>","DOI":"10.1155\/1994\/56371","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"89-103","source":"Crossref","is-referenced-by-count":0,"title":["Technology Mapping for FPGA Using GeneralizedFunctional Decomposition"],"prefix":"10.1155","volume":"2","author":[{"given":"Kuo-Hua","family":"Wang","sequence":"first","affiliation":[]},{"given":"Cheng","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ting Ting","family":"Hwang","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1994,1]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/056371.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/1994\/056371.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/56371","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T03:50:40Z","timestamp":1723089040000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/56371"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,1]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/56371"],"URL":"https:\/\/doi.org\/10.1155\/1994\/56371","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1994,1]]}}}