{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T05:10:02Z","timestamp":1723093802068},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":2699,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"We present a new approach to the problem of register\u2010transfer level design optimization of pipelined data paths.\nThe output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps,\nand a fixed set of hardware operators. In order to obtain a register\u2010transfer level design, we must assign operations\nto specific operators, values to registers, and finish the interconnections. We first perform module assignment\nwith the goal of minimizing the interconnect requirements between RT\u2010level components as a preprocessing\nprocedure to the RT\u2010level design. This will result in a smaller netlist which makes the design more compact and\nthe design process more efficient. In addition to reducing the total number of interconnects, this approach will\nalso reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs\nof shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We\ndeveloped a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30\u201350 times faster than other existing heuristics while still producing better results for our purposes. Using this\nprocedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size\npipelined designs. This efficient approach will enable designers to explore a larger portion of the design space\nand trade off various design parameters effectively.<\/jats:p>","DOI":"10.1155\/1994\/43564","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"17-32","source":"Crossref","is-referenced-by-count":1,"title":["Register\u2010Transfer Synthesis of Pipelined Data Paths"],"prefix":"10.1155","volume":"2","author":[{"given":"Nohbyung","family":"Park","sequence":"first","affiliation":[]},{"given":"Fadi J.","family":"Kurdahi","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1992,8,11]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/043564.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/43564","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:44:19Z","timestamp":1723092259000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/43564"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1992,8,11]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/43564"],"URL":"https:\/\/doi.org\/10.1155\/1994\/43564","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1992,8,11]]}}}