{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T00:10:08Z","timestamp":1723075808393},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":3462,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"Ohio State Research Challenge","award":["660808"]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[1994,1]]},"abstract":"An efficient, unified algorithm, Advanced Two-Phase Cluster Partitioning<\/jats:italic>, is proposed for automated synthesis\nof pseudo\u2010exhaustive test generator for Built\u2010In Self\u2010Test (BIST) design. A prototype of the algorithm, Two-Phase Cluster Partitioning<\/jats:italic>, has been proposed and the hierarchical design procedure is computationally efficient\nand produces test generation circuitry with low hardware overhead. However, in certain worst case, the algorithm\nmay generate a sub\u2010optimal design which requires more test patterns and\/or hardware overhead. In order to\ngenerate a globally optimal design, further improvement of two\u2010phase algorithm can be achieved by expanding\nthe design space for the formation of linear sum so that the number of test signals required for pseudo\u2010exhaustive\ntesting can be reduced. We demonstrate the effectiveness of our approach by presenting detailed comparisons of\nour results against those that would be obtained by existing techniques.<\/jats:p>","DOI":"10.1155\/1994\/25656","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:56:35Z","timestamp":1190120195000},"page":"185-198","source":"Crossref","is-referenced-by-count":0,"title":["Partitioning Techniques for Built\u2010In Self\u2010Test Design"],"prefix":"10.1155","volume":"2","author":[{"given":"Chien-In Henry","family":"Chen","sequence":"first","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1990,7,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/1994\/025656.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/1994\/25656","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T23:53:14Z","timestamp":1723074794000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/1994\/25656"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1990,7,10]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[1994,1]]}},"alternative-id":["10.1155\/1994\/25656"],"URL":"https:\/\/doi.org\/10.1155\/1994\/25656","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1990,7,10]]}}}