{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T22:50:26Z","timestamp":1730328626461,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[1989,4]]},"DOI":"10.1145\/70082.68204","type":"proceedings-article","created":{"date-parts":[[2004,2,3]],"date-time":"2004-02-03T10:24:38Z","timestamp":1075803878000},"page":"230-242","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":31,"title":["Evaluating the performance of software cache coherence"],"prefix":"10.1145","author":[{"given":"S.","family":"Owicki","sequence":"first","affiliation":[{"name":"Systems Research Center, Digital Equipment Corporation, Palo Alto, CA"}]},{"given":"A.","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, MA"}]}],"member":"320","published-online":{"date-parts":[[1989,4]]},"reference":[{"key":"e_1_3_2_1_1_2","doi-asserted-by":"publisher","DOI":"10.1145\/55595.55620"},{"key":"e_1_3_2_1_2_2","volume-title":"Mark Hotowitz. An Evaluation of Directory Schemes for Cache Coherence. In Proceedings of the 15th international Symposium on Computer Architecture","author":"Agarwal Anent","year":"1988","unstructured":"Anent Agarwal , Richard Simoni , John Hennessy , and Mark Hotowitz. An Evaluation of Directory Schemes for Cache Coherence. In Proceedings of the 15th international Symposium on Computer Architecture , June 1988 . Anent Agarwal, Richard Simoni, John Hennessy, and Mark Hotowitz. An Evaluation of Directory Schemes for Cache Coherence. In Proceedings of the 15th international Symposium on Computer Architecture, June 1988."},{"key":"e_1_3_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/6513.6514"},{"key":"e_1_3_2_1_4_2","first-page":"782","volume-title":"Proceedings 1985 Int'l Conference on Parallel Processing","author":"Brantley W. C.","year":"1985","unstructured":"W. C. Brantley , K. P. McAuliffe , and J. Weiss . RP3 Processor-Memory Element . In Proceedings 1985 Int'l Conference on Parallel Processing , pages 782 - 789 , 1985 . W. C. Brantley, K. P. McAuliffe, and J. Weiss. RP3 Processor-Memory Element. In Proceedings 1985 Int'l Conference on Parallel Processing, pages 782-789, 1985."},{"key":"e_1_3_2_1_5_2","article-title":"A New Solution to Coherence Problems in Multicache Systems","volume":"1112","author":"Censier Lucien M.","year":"1978","unstructured":"Lucien M. Censier and Paul Feautrier . A New Solution to Coherence Problems in Multicache Systems . IEEE Transactions on Computers, c-27(12) : 1112-1118 , December 1978 . Lucien M. Censier and Paul Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers, c-27(12):1112-1118, December 1978.","journal-title":"IEEE Transactions on Computers, c-27(12)"},{"key":"e_1_3_2_1_6_2","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52434"},{"key":"e_1_3_2_1_7_2","doi-asserted-by":"publisher","DOI":"10.5555\/17407.17399"},{"key":"e_1_3_2_1_8_2","volume-title":"Proceedings ICPP","author":"Cytron Ron","year":"1988","unstructured":"Ron Cytron , Steve Katlovsky , and Herin P . McAuliffe. Automatic Management of Programmable Caches . In Proceedings ICPP , August 1988 . Ron Cytron, Steve Katlovsky, and Herin P. McAuliffe. Automatic Management of Programmable Caches. In Proceedings ICPP, August 1988."},{"key":"e_1_3_2_1_9_2","doi-asserted-by":"publisher","DOI":"10.5555\/327010.327143"},{"key":"e_1_3_2_1_10_2","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52442"},{"key":"e_1_3_2_1_11_2","first-page":"764","volume-title":"Proceedings ICPP","author":"G. F.","year":"1985","unstructured":"G. F. Pfister et. el. The IBM Research Parallel Processot Prototype (RP3): Introduction and Architecture . In Proceedings ICPP , pages 764 - 771 , August 1985 . G. F. Pfister et. el. The IBM Research Parallel Processot Prototype (RP3): Introduction and Architecture. In Proceedings ICPP, pages 764-771, August 1985."},{"key":"e_1_3_2_1_12_2","first-page":"1","volume":"57","author":"S","year":"1984","unstructured":"S . J. Frank. Tightly Coupled Multiprocessor System Speeds Up Memory Access Times. Electronics , 57 , 1 , January 1984 . S. J. Frank. Tightly Coupled Multiprocessor System Speeds Up Memory Access Times. Electronics, 57, 1, January 1984.","journal-title":"J. Frank. Tightly Coupled Multiprocessor System Speeds Up Memory Access Times. Electronics"},{"key":"e_1_3_2_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/800123.803967"},{"key":"e_1_3_2_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/800046.801647"},{"key":"e_1_3_2_1_16_2","volume-title":"Proceedings of Perforrnance 87","author":"Greenberg Albert G.","year":"1987","unstructured":"Albert G. Greenberg , Isi Mitrani , and Larry Rudolph . AnMysis of snooping caches . In Proceedings of Perforrnance 87 , l~th int'l Syrup. on Computer Performance , December 1987 . Albert G. Greenberg, Isi Mitrani, and Larry Rudolph. AnMysis of snooping caches. In Proceedings of Perforrnance 87, l~th int'l Syrup. on Computer Performance, December 1987."},{"key":"e_1_3_2_1_18_2","doi-asserted-by":"publisher","DOI":"10.5555\/327010.327237"},{"key":"e_1_3_2_1_19_2","article-title":"The Performance of Multistage interconnection Networks for Multiprocessots","volume":"1091","author":"Kruskal Clyde P.","year":"1983","unstructured":"Clyde P. Kruskal and Marc Snir . The Performance of Multistage interconnection Networks for Multiprocessots . IEEE Transactions on Computers, c-32(12) : 1091- 1098 , December 1983 . Clyde P. Kruskal and Marc Snir. The Performance of Multistage interconnection Networks for Multiprocessots. IEEE Transactions on Computers, c-32(12):1091- 1098, December 1983.","journal-title":"IEEE Transactions on Computers, c-32(12)"},{"key":"e_1_3_2_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1975.224157"},{"key":"e_1_3_2_1_21_2","volume-title":"Quantitative System Performance","author":"Lazowska Edward D.","year":"1984","unstructured":"Edward D. Lazowska , John Zahorjan , G. Scott Graham , and Kenneth C. Sevcik . Quantitative System Performance . Prentice Hall , 1984 . Edward D. Lazowska, John Zahorjan, G. Scott Graham, and Kenneth C. Sevcik. Quantitative System Performance. Prentice Hall, 1984."},{"key":"e_1_3_2_1_23_2","first-page":"458","volume-title":"Proceedings of Spring COMPCON","author":"McGrogan Steve","year":"1986","unstructured":"Steve McGrogan , Robert Olson , and Nell Toda . Parallelizing large existing programs- methodology and experiences . In Proceedings of Spring COMPCON , pages 458 - 466 , March 1986 . Steve McGrogan, Robert Olson, and Nell Toda. Parallelizing large existing programs- methodology and experiences. In Proceedings of Spring COMPCON, pages 458-466, March 1986."},{"key":"e_1_3_2_1_24_2","volume-title":"July","author":"Olson Robert","year":"1985","unstructured":"Robert Olson . Parallel Processing in a Message-Based Operating System. iEEE So\/tware , July 1985 . Robert Olson. Parallel Processing in a Message-Based Operating System. iEEE So\/tware, July 1985."},{"key":"e_1_3_2_1_25_2","article-title":"Analysis of Multiprocessors with Prk v ate Cache Memories","volume":"296","author":"Patel Janak H.","year":"1982","unstructured":"Janak H. Patel . Analysis of Multiprocessors with Prk v ate Cache Memories . IEEE Transactions on Computers, c-31(4) : 296-304 , April 1982 . Janak H. Patel. Analysis of Multiprocessors with Prk v ate Cache Memories. IEEE Transactions on Computers, c-31(4):296-304, April 1982.","journal-title":"IEEE Transactions on Computers, c-31(4)"},{"key":"e_1_3_2_1_26_2","article-title":"Performance of Processor-Memory Interconnections for Multiprocessors","volume":"771","author":"Patel Janak H.","year":"1981","unstructured":"Janak H. Patel . Performance of Processor-Memory Interconnections for Multiprocessors . IEEE Transactions on Computers, c-30(10) : 771-780 , October 1981 . Janak H. Patel. Performance of Processor-Memory Interconnections for Multiprocessors. IEEE Transactions on Computers, c-30(10):771-780, October 1981.","journal-title":"IEEE Transactions on Computers, c-30(10)"},{"key":"e_1_3_2_1_27_2","volume-title":"Proceedings of the 15th International Symposium on Computer Architecture","author":"Richard","year":"1988","unstructured":"Richard L. Sites and Anant AgarwaJ. Multiprocessor Cache Analysis using ATUM . In Proceedings of the 15th International Symposium on Computer Architecture , June 1988 . Richard L. Sites and Anant AgarwaJ. Multiprocessor Cache Analysis using ATUM. In Proceedings of the 15th International Symposium on Computer Architecture, June 1988."},{"key":"e_1_3_2_1_28_2","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"},{"key":"e_1_3_2_1_29_2","volume-title":"Jay Smith. CPU Cache Consistency with Software Support and Using One Time Identifiers. In Proceedings of the Pacific Computer Communications Symposium","author":"Alan","year":"1985","unstructured":"Alan Jay Smith. CPU Cache Consistency with Software Support and Using One Time Identifiers. In Proceedings of the Pacific Computer Communications Symposium , October 1985 . Alan Jay Smith. CPU Cache Consistency with Software Support and Using One Time Identifiers. In Proceedings of the Pacific Computer Communications Symposium, October 1985."},{"key":"e_1_3_2_1_30_2","first-page":"749","volume-title":"Cache Design in the Tightly Coupled Multiprocessor System. In AFIPS Conference Proceedings, National Computer Con\/erence, NY, NY","author":"Tang C. K.","year":"1976","unstructured":"C. K. Tang . Cache Design in the Tightly Coupled Multiprocessor System. In AFIPS Conference Proceedings, National Computer Con\/erence, NY, NY , pages 749 - 753 , June 1976 . C. K. Tang. Cache Design in the Tightly Coupled Multiprocessor System. In AFIPS Conference Proceedings, National Computer Con\/erence, NY, NY, pages 749- 753, June 1976."},{"key":"e_1_3_2_1_31_2","doi-asserted-by":"publisher","DOI":"10.1145\/36206.36199"},{"key":"e_1_3_2_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/317499.317534"},{"key":"e_1_3_2_1_33_2","doi-asserted-by":"publisher","DOI":"10.5555\/52400.52435"}],"event":{"name":"ASPLOS89: Int'l Conference on Architecture Support for Programming Lang & Operating Systems","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","IEEE-CS Computer Society"],"location":"Boston Massachusetts USA","acronym":"ASPLOS89"},"container-title":["Proceedings of the third international conference on Architectural support for programming languages and operating systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/70082.68204","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T08:02:24Z","timestamp":1693814544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/70082.68204"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1989,4]]},"references-count":30,"alternative-id":["10.1145\/70082.68204","10.1145\/70082"],"URL":"https:\/\/doi.org\/10.1145\/70082.68204","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/68182.68204","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[1989,4]]},"assertion":[{"value":"1989-04-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}