{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T22:22:36Z","timestamp":1730326956097,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":107,"publisher":"ACM","funder":[{"DOI":"10.13039\/100016682","name":"VMware","doi-asserted-by":"publisher","award":["Early Career Faculty"],"id":[{"id":"10.13039\/100016682","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","award":["Allocamelus"],"id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003246","name":"Nederlandse Organisatie voor Wetenschappelijk Onderzoek","doi-asserted-by":"publisher","award":["Intersect"],"id":[{"id":"10.13039\/501100003246","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100015798","name":"SBA Research","doi-asserted-by":"publisher","award":["Competence Centers for Excellent Technologies"],"id":[{"id":"10.13039\/501100015798","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,10,16]]},"DOI":"10.1145\/3607199.3607248","type":"proceedings-article","created":{"date-parts":[[2023,10,3]],"date-time":"2023-10-03T22:30:51Z","timestamp":1696372251000},"page":"207-221","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Quarantine: Mitigating Transient Execution Attacks with Physical Domain Isolation"],"prefix":"10.1145","author":[{"ORCID":"http:\/\/orcid.org\/0009-0008-4912-414X","authenticated-orcid":false,"given":"Math\u00e9","family":"Hertogh","sequence":"first","affiliation":[{"name":"Vrije Universiteit Amsterdam, Netherlands"}]},{"ORCID":"http:\/\/orcid.org\/0009-0003-1988-1362","authenticated-orcid":false,"given":"Manuel","family":"Wiesinger","sequence":"additional","affiliation":[{"name":"Vrije Universiteit Amsterdam, Netherlands"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-0636-9848","authenticated-orcid":false,"given":"Sebastian","family":"\u00d6sterlund","sequence":"additional","affiliation":[{"name":"Intel Corporation, Netherlands"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-3393-5123","authenticated-orcid":false,"given":"Marius","family":"Muench","sequence":"additional","affiliation":[{"name":"Vrije Universiteit Amsterdam, United Kingdom"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-6643-6232","authenticated-orcid":false,"given":"Nadav","family":"Amit","sequence":"additional","affiliation":[{"name":"VMware Research, USA"}]},{"ORCID":"http:\/\/orcid.org\/0000-0001-6179-1510","authenticated-orcid":false,"given":"Herbert","family":"Bos","sequence":"additional","affiliation":[{"name":"Vrije Universiteit Amsterdam, Netherlands"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-8329-5929","authenticated-orcid":false,"given":"Cristiano","family":"Giuffrida","sequence":"additional","affiliation":[{"name":"Vrije Universiteit Amsterdam, Netherlands"}]}],"member":"320","published-online":{"date-parts":[[2023,10,16]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Amazon. 2020. Flushing L1d On Context Switches. https:\/\/www.phoronix.com\/scan.php?page=news_item&px=Linux-Blasts-L1d-Flushing."},{"volume-title":"2011 USENIX Annual Technical Conference (USENIX ATC 11)","year":"2011","author":"Amit Nadav","key":"e_1_3_2_1_2_1","unstructured":"Nadav Amit, Muli Ben-Yehuda, IBM Research, Dan Tsafrir, and Assaf Schuster. 2011. vIOMMU: Efficient IOMMU Emulation. In 2011 USENIX Annual Technical Conference (USENIX ATC 11). USENIX Association, Portland, OR. https:\/\/www.usenix.org\/conference\/usenixatc11\/viommu-efficient-iommu-emulation"},{"volume-title":"31st USENIX Security Symposium (USENIX Security 22)","year":"2022","author":"Barberis Enrico","key":"e_1_3_2_1_3_1","unstructured":"Enrico Barberis, Pietro Frigo, Marius Muench, Herbert Bos, and Cristiano Giuffrida. 2022. Branch History Injection: On the Effectiveness of Hardware Mitigations Against Cross-Privilege Spectre-v2 Attacks. In 31st USENIX Security Symposium (USENIX Security 22). USENIX Association, Boston, MA, 971\u2013988. https:\/\/www.usenix.org\/conference\/usenixsecurity22\/presentation\/barberis"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/3492321.3519559"},{"volume-title":"14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20)","year":"2020","author":"Behrens Jonathan","key":"e_1_3_2_1_5_1","unstructured":"Jonathan Behrens, Anton Cao, Cel Skeggs, Adam Belay, M.\u00a0Frans Kaashoek, and Nickolai Zeldovich. 2020. Efficiently Mitigating Transient Execution Attacks using the Unmapped Speculation Contract. In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). USENIX Association, 1139\u20131154. https:\/\/www.usenix.org\/conference\/osdi20\/presentation\/behrens"},{"volume-title":"2005 USENIX Annual Technical Conference (USENIX ATC 05)","year":"2005","author":"Bellard Fabrice","key":"e_1_3_2_1_6_1","unstructured":"Fabrice Bellard. 2005. QEMU, a Fast and Portable Dynamic Translator. In 2005 USENIX Annual Technical Conference (USENIX ATC 05). USENIX Association, Anaheim, CA. https:\/\/www.usenix.org\/conference\/2005-usenix-annual-technical-conference\/qemu-fast-and-portable-dynamic-translator"},{"volume-title":"28th USENIX Security Symposium (USENIX Security 19)","year":"2019","author":"Canella Claudio","key":"e_1_3_2_1_7_1","unstructured":"Claudio Canella, Jo\u00a0Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019. A Systematic Evaluation of Transient Execution Attacks and Defenses. In 28th USENIX Security Symposium (USENIX Security 19). USENIX Association, Santa Clara, CA, 249\u2013266. https:\/\/www.usenix.org\/conference\/usenixsecurity19\/presentation\/canella"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/3319535.3363219"},{"key":"e_1_3_2_1_9_1","unstructured":"Alexandre Chartre. 2022. Address Space Isolation for KVM. https:\/\/lore.kernel.org\/lkml\/91dd5f0a-61da-074d-42ed-bf0886f617d9@oracle.com\/"},{"key":"e_1_3_2_1_10_1","unstructured":"Jonathan Corbet. 2021. memfd_secret() in 5.14. https:\/\/lwn.net\/Articles\/837595\/"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","unstructured":"Albert Danial. 2021. cloc: v1.92. https:\/\/doi.org\/10.5281\/zenodo.5760077","DOI":"10.5281\/zenodo.5760077"},{"key":"e_1_3_2_1_12_1","unstructured":"[12] Linux Developers. 2020. https:\/\/www.kernel.org\/doc\/html\/latest\/admin-guide\/hw-vuln\/core-scheduling.html#protecting-the-kernel-irq-syscall-vmexit"},{"key":"e_1_3_2_1_13_1","unstructured":"Linux\u00a0Kernel Developers. 2019. Spectre Side Channels - Linux Kernel Documentation. https:\/\/www.kernel.org\/doc\/html\/v5.15\/admin-guide\/hw-vuln\/spectre.html"},{"volume-title":"Core scheduling (v9). (Nov","year":"2020","author":"Fernandes Joel","key":"e_1_3_2_1_14_1","unstructured":"Joel Fernandes. 2020. Core scheduling (v9). (Nov 2020). https:\/\/lore.kernel.org\/all\/20201117232003.3580179-1-joel@joelfernandes.org\/"},{"volume-title":"Workshop on system-level virtualization for HPC (HPCVirt). Citeseer.","year":"2007","author":"Gavrilovska Ada","key":"e_1_3_2_1_15_1","unstructured":"Ada Gavrilovska, Sanjay Kumar, Himanshu Raj, Karsten Schwan, Vishakha Gupta, Ripal Nathuji, Radhika Niranjan, Adit Ranadive, and Purav Saraiya. 2007. High-performance hypervisor architectures: Virtualization in hpc systems. In Workshop on system-level virtualization for HPC (HPCVirt). Citeseer."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303976"},{"key":"e_1_3_2_1_17_1","unstructured":"Will Glozer. 2012. wrk - a HTTP benchmarking tool. https:\/\/github.com\/wg\/wrk"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3372297.3417289"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2367589.2367593"},{"volume-title":"2013 USENIX Annual Technical Conference (USENIX ATC 13)","year":"2013","author":"Har\u2019El Nadav","key":"e_1_3_2_1_20_1","unstructured":"Nadav Har\u2019El, Abel Gordon, Alex Landau, Muli Ben-Yehuda, Avishay Traeger, and Razya Ladelsky. 2013. Efficient and Scalable Paravirtual I\/O System. In 2013 USENIX Annual Technical Conference (USENIX ATC 13). USENIX Association, San Jose, CA, 231\u2013242."},{"key":"e_1_3_2_1_21_1","unstructured":"Jann Horn. 2018. Speculative Store Bypass. https:\/\/bugs.chromium.org\/p\/project-zero\/issues\/detail?id=1528."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2354410.2355161"},{"key":"e_1_3_2_1_23_1","unstructured":"Intel. 2018. Bounds Check Bypass. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/bounds-check-bypass.html"},{"key":"e_1_3_2_1_24_1","unstructured":"Intel. 2018. Branch Target Injection. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/branch-target-injection.html"},{"key":"e_1_3_2_1_25_1","unstructured":"Intel. 2018. Indirect Branch Restricted Speculation. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/technical-documentation\/indirect-branch-restricted-speculation.html"},{"key":"e_1_3_2_1_26_1","unstructured":"Intel. 2018. L1 Terminal Fault. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/l1-terminal-fault.html"},{"key":"e_1_3_2_1_27_1","unstructured":"Intel. 2018. Lazy FP state restore. https:\/\/www.intel.com\/content\/www\/us\/en\/security-center\/advisory\/intel-sa-00145.html"},{"key":"e_1_3_2_1_28_1","unstructured":"Intel. 2018. Rogue Data Cache Load. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/rogue-data-cache-load.html"},{"key":"e_1_3_2_1_29_1","unstructured":"Intel. 2018. Rogue System Register Read. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/rogue-system-register-read.html"},{"key":"e_1_3_2_1_30_1","unstructured":"Intel. 2018. Speculative Store Bypass. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/speculative-store-bypass.html"},{"key":"e_1_3_2_1_31_1","unstructured":"Intel. 2019. Intel Transactional Synchronization Extensions (Intel TSX) Asynchronous Abort. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/intel-tsx-asynchronous-abort.html"},{"key":"e_1_3_2_1_32_1","unstructured":"Intel. 2019. Microarchitectural Data Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/microarchitectural-data-sampling.html"},{"key":"e_1_3_2_1_33_1","unstructured":"Intel. 2019. Speculative Behavior of SWAPGS and Segment Registers. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/speculative-behavior-swapgs-and-segment-registers.html"},{"key":"e_1_3_2_1_34_1","unstructured":"Intel. 2020. L1D Eviction Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/l1d-eviction-sampling.html"},{"key":"e_1_3_2_1_35_1","unstructured":"Intel. 2020. Load Value Injection. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/load-value-injection.html"},{"key":"e_1_3_2_1_36_1","unstructured":"Intel. 2020. Snoop-assisted L1 Data Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/snoop-assisted-l1-data-sampling.html"},{"key":"e_1_3_2_1_37_1","unstructured":"Intel. 2020. Special Register Buffer Data Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/special-register-buffer-data-sampling.html"},{"key":"e_1_3_2_1_38_1","unstructured":"Intel. 2020. Vector Register Sampling. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/vector-register-sampling.html"},{"key":"e_1_3_2_1_39_1","unstructured":"Intel. 2021. Floating Point Value Injection. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/floating-point-value-injection.html"},{"key":"e_1_3_2_1_40_1","unstructured":"Intel. 2021. Microarchitectural Data Sampling (MDS) Version: 3.0. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/technical-documentation\/intel-analysis-microarchitectural-data-sampling.html."},{"key":"e_1_3_2_1_41_1","unstructured":"Intel. 2021. Speculative Code Store Bypass. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/speculative-code-store-bypass.html"},{"key":"e_1_3_2_1_42_1","unstructured":"Intel. 2022. Branch History Injection and Intra-mode Branch Target Injection. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/branch-history-injection.html"},{"key":"e_1_3_2_1_43_1","unstructured":"Intel. 2022. Fast Store Forwarding Predictor. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/technical-documentation\/fast-store-forwarding-predictor.html"},{"key":"e_1_3_2_1_44_1","unstructured":"Intel. 2022. Post-barrier Return Stack Buffer Predictions. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/post-barrier-return-stack-buffer-predictions.html"},{"key":"e_1_3_2_1_45_1","unstructured":"Intel. 2022. Processor MMIO Stale Data Vulnerabilities. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/processor-mmio-stale-data-vulnerabilities.html"},{"key":"e_1_3_2_1_46_1","unstructured":"Intel. 2022. Return Stack Buffer Underflow. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/return-stack-buffer-underflow.html"},{"key":"e_1_3_2_1_47_1","unstructured":"Intel. 2022. Speculative Load Disordering. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/advisory-guidance\/speculative-load-disordering.html"},{"volume-title":"Kasper: Scanning for Generalized Transient Execution Gadgets in the Linux Kernel. In NDSS.","year":"2022","author":"Johannesmeyer Brian","key":"e_1_3_2_1_48_1","unstructured":"Brian Johannesmeyer, Jakob Koschel, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2022. Kasper: Scanning for Generalized Transient Execution Gadgets in the Linux Kernel. In NDSS."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816010"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00083"},{"key":"e_1_3_2_1_51_1","unstructured":"Vladimir Kiriansky and Carl Waldspurger. 2018. Speculative Buffer Overflows: Attacks and Defenses. arxiv:1807.03757\u00a0[cs.CR]"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"volume-title":"12th USENIX Workshop on Offensive Technologies (WOOT 18)","year":"2018","author":"Koruyeh Esmaeil\u00a0Mohammadian","key":"e_1_3_2_1_53_1","unstructured":"Esmaeil\u00a0Mohammadian Koruyeh, Khaled\u00a0N. Khasawneh, Chengyu Song, and Nael Abu-Ghazaleh. 2018. Spectre Returns! Speculation Attacks using the Return Stack Buffer. In 12th USENIX Workshop on Offensive Technologies (WOOT 18). USENIX Association, Baltimore, MD. https:\/\/www.usenix.org\/conference\/woot18\/presentation\/koruyeh"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3447786.3456248"},{"volume-title":"Workshop on Interaction between Opearting Systems & Computer Architecture (WIOSCA). Citeseer.","year":"2007","author":"Kumar Sanjay","key":"e_1_3_2_1_55_1","unstructured":"Sanjay Kumar, Himanshu Raj, Karsten Schwan, and Ivan Ganev. 2007. Re-architecting VMMs for multicore systems: The sidecore approach. In Workshop on Interaction between Opearting Systems & Computer Architecture (WIOSCA). Citeseer."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/3342195.3387526"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/2980024.2872378"},{"volume-title":"SplitX: Split Guest\/Hypervisor Execution on Multi-Core. In 3rd Workshop on I\/O Virtualization (WIOV 11)","year":"2011","author":"Landau Alex","key":"e_1_3_2_1_58_1","unstructured":"Alex Landau, Muli Ben-Yehuda, and Abel Gordon. 2011. SplitX: Split Guest\/Hypervisor Execution on Multi-Core. In 3rd Workshop on I\/O Virtualization (WIOV 11). USENIX Association, Portland, OR. https:\/\/www.usenix.org\/conference\/wiov11\/splitx-split-guesthypervisor-execution-multi-core"},{"volume-title":"Bisected: The Unfortunate Reason Linux 4.20 Is Running Slower. https:\/\/www.phoronix.com\/scan.php?page=article&item=linux-420-bisect.","year":"2018","author":"Larabel Michael","key":"e_1_3_2_1_59_1","unstructured":"Michael Larabel. 2018. Bisected: The Unfortunate Reason Linux 4.20 Is Running Slower. https:\/\/www.phoronix.com\/scan.php?page=article&item=linux-420-bisect."},{"key":"e_1_3_2_1_60_1","unstructured":"Michael Larabel. 2020. The Brutal Performance Impact From Mitigating The LVI Vulnerability. https:\/\/www.phoronix.com\/review\/lvi-attack-perf."},{"key":"e_1_3_2_1_61_1","unstructured":"Michael Larabel. 2022. Call Depth Tracking For Less Costly Retbleed Mitigation Hopes To Land Soon. https:\/\/www.phoronix.com\/news\/Call-Depth-Tracking-Hope-Soon"},{"key":"e_1_3_2_1_62_1","unstructured":"Michael Larabel. 2022. In Light Of Spectre BHI The Performance Impact For Retpolines On Modern Intel CPUs. https:\/\/www.phoronix.com\/scan.php?page=article&item=spectre-bhi-retpoline&num=1."},{"volume-title":"vCanal: Paravirtual Socket Library towards Fast Networking in Virtualized Environment. IEICE TRANSACTIONS on Information and Systems 99, 2","year":"2016","author":"Lee Dongwoo","key":"e_1_3_2_1_63_1","unstructured":"Dongwoo Lee, Changwoo Min, and Young\u00a0Ik Eom. 2016. vCanal: Paravirtual Socket Library towards Fast Networking in Virtualized Environment. IEICE TRANSACTIONS on Information and Systems 99, 2 (2016)."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/1281700.1281702"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/3357033"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446082"},{"volume-title":"Proceedings of the 23rd international conference on Supercomputing.","year":"2009","author":"Liu Jiuxing","key":"e_1_3_2_1_67_1","unstructured":"Jiuxing Liu and Bulent Abali. 2009. Virtualization polling engine (VPE) using dedicated CPU cores to accelerate I\/O virtualization. In Proceedings of the 23rd international conference on Supercomputing."},{"key":"e_1_3_2_1_68_1","unstructured":"Anil Madhavapeddy Thomas Leonard Magnus Skjegstad Thomas Gazagnaire David Sheets Dave Scott Richard Mortier Amir Chaudhry Balraj Singh Jon Ludlam 2015. Jitsu:Just-In-Time Summoning of Unikernels. In NSDI."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451167"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-40965-6_2"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"crossref","unstructured":"Giorgi Maisuradze and Christian Rossow. 2018. ret2spec: Speculative Execution using Return Stack Buffers. (2018).","DOI":"10.1145\/3243734.3243761"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"crossref","unstructured":"Filipe Manco Costin Lupu Florian Schmidt Jose Mendes Simon Kuenzer Sumit Sati Kenichi Yasukata Costin Raiciu and Felipe Huici. 2017. My VM is Lighter (and Safer) than your Container. In SOSP.","DOI":"10.1145\/3132747.3132763"},{"volume-title":"USENIX annual technical conference.","author":"McVoy W","key":"e_1_3_2_1_73_1","unstructured":"Larry\u00a0W McVoy, Carl Staelin, 1996. LMbench: Portable Tools for Performance Analysis.. In USENIX annual technical conference. San Diego, CA, USA."},{"volume-title":"You cannot always win the race: Analyzing the lfence\/jmp mitigation for branch target injection. arXiv preprint arXiv:2203.04277","year":"2022","author":"Milburn Alyssa","key":"e_1_3_2_1_74_1","unstructured":"Alyssa Milburn, Ke Sun, and Henrique Kawakami. 2022. You cannot always win the race: Analyzing the lfence\/jmp mitigation for branch target injection. arXiv preprint arXiv:2203.04277 (2022)."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2856125"},{"key":"e_1_3_2_1_76_1","unstructured":"Ingo Molnar and Max Krasnyansky. 2020. SMP IRQ affinity. https:\/\/docs.kernel.org\/core-api\/irq\/irq-affinity.html."},{"volume-title":"Nomad: Mitigating arbitrary cloud side channels via provider-assisted migration. In CCS.","year":"2015","author":"Moon Soo-Jin","key":"e_1_3_2_1_77_1","unstructured":"Soo-Jin Moon, Vyas Sekar, and Michael\u00a0K Reiter. 2015. Nomad: Mitigating arbitrary cloud side channels via provider-assisted migration. In CCS."},{"volume-title":"Intel CPUs Lose Up to 36% Performance with New Spectre Patch. The FPS Review (Mar","year":"2022","author":"Mui Tsing","key":"e_1_3_2_1_78_1","unstructured":"Tsing Mui. 2022. Intel CPUs Lose Up to 36% Performance with New Spectre Patch. The FPS Review (Mar 2022)."},{"volume-title":"29th USENIX Security Symposium (USENIX Security 20)","year":"2020","author":"Oleksenko Oleksii","key":"e_1_3_2_1_79_1","unstructured":"Oleksii Oleksenko, Bohdan Trach, Mark Silberstein, and Christof Fetzer. 2020. SpecFuzz: Bringing Spectre-type vulnerabilities to the surface. In 29th USENIX Security Symposium (USENIX Security 20). USENIX Association, 1481\u20131498. https:\/\/www.usenix.org\/conference\/usenixsecurity20\/presentation\/oleksenko"},{"volume-title":"USENIX Security Symposium. 645\u2013662","year":"2021","author":"Paccagnella Riccardo","key":"e_1_3_2_1_80_1","unstructured":"Riccardo Paccagnella, Licheng Luo, and Christopher\u00a0W Fletcher. 2021. Lord of the Ring (s): Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practical.. In USENIX Security Symposium. 645\u2013662."},{"key":"e_1_3_2_1_81_1","first-page":"651","article-title":"MFENCE and LFENCE Micro-Architectural Implementation Method and System","volume":"6","author":"Palanca Salvador","year":"2002","unstructured":"Salvador Palanca, Stephen A.\u00a0Fischer, Subramaniam Maiyuran, and Shekoufeh Qawami. 2002. MFENCE and LFENCE Micro-Architectural Implementation Method and System. US Patent 6,651,151.","journal-title":"US Patent"},{"volume-title":"USENIX Security Symposium. 565\u2013581","year":"2016","author":"Pessl Peter","key":"e_1_3_2_1_82_1","unstructured":"Peter Pessl, Daniel Gruss, Cl\u00e9mentine Maurice, Michael Schwarz, and Stefan Mangard. 2016. DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks.. In USENIX Security Symposium. 565\u2013581."},{"key":"e_1_3_2_1_83_1","unstructured":"Zhenxiao Qi Qian Feng Yueqiang Cheng Mengjia Yan Peng Li Heng Yin and Tao Wei. 2021. SpecTaint: Speculative Taint Analysis for Discovering Spectre Gadgets.. In NDSS."},{"key":"e_1_3_2_1_84_1","unstructured":"Hany Ragab Enrico Barberis Herbert Bos and Cristiano Giuffrida. 2021. Rage Against the Machine Clear: A Systematic Analysis of Machine Clears and Their Implications for Transient Execution Attacks. In USENIX Security."},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"crossref","unstructured":"Hany Ragab Alyssa Milburn Kaveh Razavi Herbert Bos and Cristiano Giuffrida. 2021. CrossTalk: Speculative Data Leaks Across Cores Are Real. In S&P. Intel Bounty Reward.","DOI":"10.1109\/SP40001.2021.00020"},{"key":"e_1_3_2_1_86_1","unstructured":"Charles Reis Alexander Moshchuk and Nasko Oskov. 2019. Site isolation: Process separation for web sites within the browser. In USENIX Security."},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00036"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1145\/3319535.3354252"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-29959-0_14"},{"key":"e_1_3_2_1_90_1","unstructured":"Junaid Shahid. 2022. Address Space Isolation for KVM. https:\/\/lore.kernel.org\/lkml\/20220223052223.1202152-1-junaids@google.com"},{"key":"e_1_3_2_1_91_1","unstructured":"Livio Soares and Michael Stumm. 2010. FlexSC: Flexible System Call Scheduling with Exception-Less System Calls. In OSDI Vol.\u00a010."},{"key":"e_1_3_2_1_92_1","unstructured":"Julian Stecklina and Thomas Prescher. 2018. LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels. (2018)."},{"key":"e_1_3_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1145\/2046707.2046754"},{"key":"e_1_3_2_1_94_1","unstructured":"Paul Turner. 2018. Retpoline: a Software Construct for Preventing Branch Target Injection. https:\/\/support.google.com\/faqs\/answer\/7625886."},{"volume-title":"Proceedings of the 27th USENIX Security Symposium. USENIX Association.","year":"2018","author":"Van\u00a0Bulck Jo","key":"e_1_3_2_1_95_1","unstructured":"Jo Van\u00a0Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas\u00a0F. Wenisch, Yuval Yarom, and Raoul Strackx. 2018. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution. In Proceedings of the 27th USENIX Security Symposium. USENIX Association."},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00089"},{"key":"e_1_3_2_1_97_1","doi-asserted-by":"crossref","unstructured":"Stephan van Schaik Alyssa Milburn Sebastian \u00d6sterlund Pietro Frigo Giorgi Maisuradze Kaveh Razavi Herbert Bos and Cristiano Giuffrida. 2019. Addendum 1 to RIDL: Rogue In-flight Data Load. In S&P.","DOI":"10.1109\/SP.2019.00087"},{"volume-title":"RIDL: Rogue In-flight Data Load. In S&P.","year":"2019","author":"van Schaik Stephan","key":"e_1_3_2_1_98_1","unstructured":"Stephan van Schaik, Alyssa Milburn, Sebastian \u00d6sterlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2019. RIDL: Rogue In-flight Data Load. In S&P."},{"key":"e_1_3_2_1_99_1","doi-asserted-by":"crossref","unstructured":"Stephan van Schaik Alyssa Milburn Sebastian \u00d6sterlund Pietro Frigo Giorgi Maisuradze Kaveh Razavi Herbert Bos and Cristiano Giuffrida. 2020. Addendum 2 to RIDL: Rogue In-flight Data Load. In S&P.","DOI":"10.1109\/SP.2019.00087"},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"crossref","unstructured":"Stephan van Schaik Marina Minkin Andrew Kwong Daniel Genkin and Yuval Yarom. 2021. CacheOut: Leaking Data on Intel CPUs via Cache Evictions. In S&P.","DOI":"10.1109\/SP40001.2021.00064"},{"volume-title":"Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution. Technical report","year":"2018","author":"Weisse Ofir","key":"e_1_3_2_1_101_1","unstructured":"Ofir Weisse, Jo Van\u00a0Bulck, Marina Minkin, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Raoul Strackx, Thomas\u00a0F. Wenisch, and Yuval Yarom. 2018. Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution. Technical report (2018)."},{"volume-title":"RETBLEED: Arbitrary Speculative Code Execution with Return Instructions. In 31st USENIX Security Symposium (USENIX Security 22)","year":"2022","author":"Wikner Johannes","key":"e_1_3_2_1_102_1","unstructured":"Johannes Wikner and Kaveh Razavi. 2022. RETBLEED: Arbitrary Speculative Code Execution with Return Instructions. In 31st USENIX Security Symposium (USENIX Security 22). USENIX Association, Boston, MA, 3825\u20133842. https:\/\/www.usenix.org\/conference\/usenixsecurity22\/presentation\/wikner"},{"volume-title":"A Secret-Free Hypervisor: Rethinking Isolation in the Age of Speculative Vulnerabilities","author":"Xia Hongyan","key":"e_1_3_2_1_103_1","unstructured":"Hongyan Xia, David Zhang, Wei Liu, Istvan Haller, Bruce Sherwin, and David Chisnall. 2022. A Secret-Free Hypervisor: Rethinking Isolation in the Age of Speculative Vulnerabilities. In IEEE S&P."},{"key":"e_1_3_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/3190508.3190511"},{"volume-title":"Survey of transient execution attacks and their mitigations. ACM Computing Surveys (CSUR) 54, 3","year":"2021","author":"Xiong Wenjie","key":"e_1_3_2_1_105_1","unstructured":"Wenjie Xiong and Jakub Szefer. 2021. Survey of transient execution attacks and their mitigations. ACM Computing Surveys (CSUR) 54, 3 (2021)."},{"volume-title":"2013 USENIX Annual Technical Conference (USENIX ATC 13)","year":"2013","author":"Xu Cong","key":"e_1_3_2_1_106_1","unstructured":"Cong Xu, Sahan Gamage, Hui Lu, Ramana Kompella, and Dongyan Xu. 2013. vTurbo: Accelerating Virtual Machine I\/O Processing Using Designated Turbo-Sliced Core. In 2013 USENIX Annual Technical Conference (USENIX ATC 13)."},{"key":"e_1_3_2_1_107_1","unstructured":"Cong Xu Karthick Rajamani Alexandre Ferreira Wesley Felter Juan Rubio and Yang Li. 2018. dcat: Dynamic cache management for efficient performance-sensitive infrastructure-as-a-service. In EuroSys."}],"event":{"name":"RAID 2023: The 26th International Symposium on Research in Attacks, Intrusions and Defenses","acronym":"RAID 2023","location":"Hong Kong China"},"container-title":["Proceedings of the 26th International Symposium on Research in Attacks, Intrusions and Defenses"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3607199.3607248","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,16]],"date-time":"2024-10-16T10:30:32Z","timestamp":1729074632000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607199.3607248"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,16]]},"references-count":107,"alternative-id":["10.1145\/3607199.3607248","10.1145\/3607199"],"URL":"https:\/\/doi.org\/10.1145\/3607199.3607248","relation":{},"subject":[],"published":{"date-parts":[[2023,10,16]]},"assertion":[{"value":"2023-10-16","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}