{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:00:37Z","timestamp":1740099637727,"version":"3.37.3"},"publisher-location":"New York, NY, USA","reference-count":58,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,3,16]],"date-time":"2021-03-16T00:00:00Z","timestamp":1615852800000},"content-version":"vor","delay-in-days":372,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"CRISP (one of six centers in JUMP a Semiconductor Research Corporation (SRC) program sponsored by MARCO and DARPA)"},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF-1629450"],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2020,3,9]]},"DOI":"10.1145\/3373376.3378459","type":"proceedings-article","created":{"date-parts":[[2020,3,13]],"date-time":"2020-03-13T22:37:01Z","timestamp":1584139021000},"page":"219-234","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators"],"prefix":"10.1145","author":[{"given":"Elaheh","family":"Sadredini","sequence":"first","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}]},{"given":"Reza","family":"Rahimi","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}]},{"given":"Marzieh","family":"Lenjani","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}]},{"given":"Mircea","family":"Stan","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}]},{"given":"Kevin","family":"Skadron","sequence":"additional","affiliation":[{"name":"University of Virginia, Charlottesville, VA, USA"}]}],"member":"320","published-online":{"date-parts":[[2020,3,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.54"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2015.2429918"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1364654.1364656"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1323548.1323573"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1477942.1477950"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445576"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636093"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00068"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2016.7840617"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2577557"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.7"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1880153.1880157"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304066"},{"key":"e_1_3_2_1_14_1","article-title":"An efficient and scalable semiconductor architecture for parallel automata processing. Parallel and Distributed Systems","volume":"25","author":"Dlugosch Paul","year":"2014","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2258247"},{"volume-title":"The abstract theory of automata. Russian Mathematical Surveys","year":"1961","author":"Glushkov Victor Mikhaylovich","key":"e_1_3_2_1_16_1"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/344166.344182"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICUFN.2013.6614821"},{"key":"e_1_3_2_1_19_1","unstructured":"Intel. [n.d.]. https:\/\/github.com\/01org\/hyperscan . Intel. [n.d.]. https:\/\/github.com\/01org\/hyperscan ."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2017.8279779"},{"volume-title":"Proceedings of the 9th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science .","author":"Vlastimil","key":"e_1_3_2_1_21_1"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00052"},{"volume-title":"An Overflow-free Quantized Memory Hierarchy in General-purpose Processors. IEEE International Symposium on Workload Characterization","year":"2019","author":"Lenjani Marzieh","key":"e_1_3_2_1_23_1"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"volume-title":"Architectural Support for Efficient Large-Scale Automata Processing. In 2018 51st Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). IEEE, 908--920","year":"2018","author":"Liu Hongyuan","key":"e_1_3_2_1_25_1"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196089"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.2011.5935024"},{"key":"e_1_3_2_1_28_1","unstructured":"Micron. 2019. RLDRAM Memory. https:\/\/www.micron.com\/products\/dram\/rldram-memory . Micron. 2019. RLDRAM Memory. https:\/\/www.micron.com\/products\/dram\/rldram-memory ."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCBB.2015.2430313"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3219819.3219889"},{"volume-title":"Impala: Algorithm\/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching. The 26th IEEE International Symposium on High-Performance Computer Architecture","year":"2020","author":"Sadredini Elaheh","key":"e_1_3_2_1_32_1"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358324"},{"volume-title":"2019 b. Scalable and Efficient in-Memory Interconnect Architecture for Automata Processing","year":"2019","author":"Sadredini Elaheh","key":"e_1_3_2_1_34_1"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079079.3079084"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1007\/10722167_21"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080207"},{"volume-title":"Cache Automaton. In 50th Annual IEEE\/ACM International Symposium on Microarchitecture .","year":"2017","author":"Subramaniyan Arun","key":"e_1_3_2_1_38_1"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-76650-6_15"},{"key":"e_1_3_2_1_40_1","unstructured":"II Tommy Tracy Mircea Stan Nathan Brunelle Jack Wadden Ke Wang Kevin Skadron and Gabriel Robins. [n.d.]. Nondeterministic finite automata in hardware-the case of the Levenshtein automaton. ( [n. d.]). II Tommy Tracy Mircea Stan Nathan Brunelle Jack Wadden Ke Wang Kevin Skadron and Gabriel Robins. [n.d.]. Nondeterministic finite automata in hardware-the case of the Levenshtein automaton. ( [n. d.])."},{"volume-title":"Proceedings of the First Symposium on Logic in Computer Science. IEEE Computer Society, 322--331","year":"1986","author":"Vardi Moshe Y","key":"e_1_3_2_1_41_1"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/bxq077"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"crossref","unstructured":"Jack Wadden et al. 2016. ANMLZoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures. In IISWC. IEEE. Jack Wadden et al. 2016. ANMLZoo: a benchmark suite for exploring bottlenecks in automata processing engines and architectures. In IISWC. IEEE.","DOI":"10.1109\/IISWC.2016.7581271"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"crossref","unstructured":"Jack Wadden et al. 2018. AutomataZoo: A Modern Automata Processing Benchmark Suite. In IISWC. IEEE. Jack Wadden et al. 2018. AutomataZoo: A Modern Automata Processing Benchmark Suite. In IISWC. IEEE.","DOI":"10.1109\/IISWC.2018.8573482"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"crossref","unstructured":"Ke Wang Kevin Angstadt Chunkun Bo Nathan Brunelle Elaheh Sadredini Tommy Tracy Jack Wadden Mircea Stan and Kevin Skadron. 2016a. An overview of micron's automata processor. In Hardware\/Software Codesign and System Synthesis (CODES Ke Wang Kevin Angstadt Chunkun Bo Nathan Brunelle Elaheh Sadredini Tommy Tracy Jack Wadden Mircea Stan and Kevin Skadron. 2016a. An overview of micron's automata processor. In Hardware\/Software Codesign and System Synthesis (CODES","DOI":"10.1145\/2968456.2976763"},{"volume-title":"2016 International Conference on. IEEE, 1--3.","key":"e_1_3_2_1_46_1"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2015.101"},{"volume-title":"International Journal of Parallel Programming (IJPP).","year":"2017","author":"Wang Ke","key":"e_1_3_2_1_48_1"},{"volume-title":"Sequential Pattern Mining with the Micron Automata Processor. In International Conference on Computing Frontiers. ACM.","year":"2016","author":"Wang Ke","key":"e_1_3_2_1_49_1"},{"volume-title":"16th $$USENIX$$ Symposium on Networked Systems Design and Implementation ($$NSDI$$ 19) . 631--648.","author":"Wang Xiang","key":"e_1_3_2_1_50_1"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056759"},{"key":"e_1_3_2_1_52_1","unstructured":"Xilinx. 2019. UltraScale Architecture Memory Resources. https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug573-ultrascale-memory-resources.pdf . Xilinx. 2019. UltraScale Architecture Memory Resources. https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug573-ultrascale-memory-resources.pdf ."},{"volume-title":"Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on. IEEE, 131--136","year":"2008","author":"Yamagaki Norio","key":"e_1_3_2_1_53_1"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.129"},{"volume-title":"ANCS 2006. ACM\/IEEE Symposium on. IEEE, 93--102","year":"2006","author":"Yu Fang","key":"e_1_3_2_1_55_1"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842846"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICOSC.2015.7050812"},{"volume-title":"First-Order vs. Second-Order Encodings for LTLf-to-Automata Translation. arXiv preprint arXiv:1901.06108","year":"2019","author":"Zhu Shufang","key":"e_1_3_2_1_58_1"}],"event":{"name":"ASPLOS '20: Architectural Support for Programming Languages and Operating Systems","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Lausanne Switzerland","acronym":"ASPLOS '20"},"container-title":["Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3373376.3378459","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3373376.3378459","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,7]],"date-time":"2023-01-07T18:19:41Z","timestamp":1673115581000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3373376.3378459"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,9]]},"references-count":58,"alternative-id":["10.1145\/3373376.3378459","10.1145\/3373376"],"URL":"https:\/\/doi.org\/10.1145\/3373376.3378459","relation":{},"subject":[],"published":{"date-parts":[[2020,3,9]]},"assertion":[{"value":"2020-03-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}