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The current state of kernel page-table isolation , https:\/\/lwn.net\/SubscriberLink\/741878\/eb6c9d3913d7cb2b\/Dec . 2017 . LWN. The current state of kernel page-table isolation, https:\/\/lwn.net\/SubscriberLink\/741878\/eb6c9d3913d7cb2b\/Dec. 2017."},{"key":"e_1_3_2_2_50_1","volume-title":"https:\/\/lwn.net\/Articles\/759423\/July","author":"Spectre","year":"2018","unstructured":"LWN. Spectre v1 defense in gcc , https:\/\/lwn.net\/Articles\/759423\/July 2018 . LWN. Spectre v1 defense in gcc, https:\/\/lwn.net\/Articles\/759423\/July 2018."},{"key":"e_1_3_2_2_51_1","volume-title":"CCS","author":"Maisuradze G.","year":"2018","unstructured":"Maisuradze , G. , and Rossow , C . ret2spec: Speculative Execution Using Return Stack Buffers . In CCS ( 2018 ). Maisuradze, G., and Rossow, C. ret2spec: Speculative Execution Using Return Stack Buffers. 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LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels. arXiv:1806.07480 (2018)."},{"key":"e_1_3_2_2_71_1","volume-title":"USENIX Security Symposium","author":"Van Bulck J.","year":"2018","unstructured":"Van Bulck , J. , Minkin , M. , Weisse , O. , Genkin , D. , Kasikci , B. , Piessens , F. , Silberstein , M. , Wenisch , T. F. , Yarom , Y. , and Strackx , R . Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution . In USENIX Security Symposium ( 2018 ). Van Bulck, J., Minkin, M., Weisse, O., Genkin, D., Kasikci, B., Piessens, F., Silberstein, M., Wenisch, T. F., Yarom, Y., and Strackx, R. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution. 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Telling your secrets without page faults: Stealthy page table-based attacks on enclaved execution. In USENIX Security Symposium (2017)."},{"key":"e_1_3_2_2_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00087"},{"key":"e_1_3_2_2_76_1","volume-title":"oo7: Low-overhead Defense against Spectre Attacks via Binary Analysis. arXiv:1807.05843","author":"Wang G.","year":"2018","unstructured":"Wang , G. , Chattopadhyay , S. , Gotovchits , I. , Mitra , T. , and Roychoudhury , A . oo7: Low-overhead Defense against Spectre Attacks via Binary Analysis. arXiv:1807.05843 ( 2018 ). Wang, G., Chattopadhyay, S., Gotovchits, I., Mitra, T., and Roychoudhury, A. oo7: Low-overhead Defense against Spectre Attacks via Binary Analysis. arXiv:1807.05843 (2018)."},{"key":"e_1_3_2_2_77_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-45744-4_22"},{"key":"e_1_3_2_2_78_1","volume-title":"Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution","author":"Weisse O.","year":"2018","unstructured":"Weisse , O. , Van Bulck , J. , Minkin , M. , Genkin , D. , Kasikci , B. , Piessens , F. , Silberstein , M. , Strackx , R. , Wenisch , T. F. , and Yarom , Y . Foreshadow-NG: Breaking the Virtual Memory Abstraction with Transient Out-of-Order Execution , 2018 . Weisse, O., Van Bulck, J., Minkin, M., Genkin, D., Kasikci, B., Piessens, F., Silberstein, M., Strackx, R., Wenisch, T. F., and Yarom, Y. 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