{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T14:33:18Z","timestamp":1725633198641},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3323484","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T14:07:13Z","timestamp":1558620433000},"page":"1-4","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Practical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing Systems"],"prefix":"10.1145","author":[{"given":"Nam Sung","family":"Kim","sequence":"first","affiliation":[{"name":"Samsung Electronics, Hwaseong, Republic of Korea"}]},{"given":"Pankaj","family":"Mehra","sequence":"additional","affiliation":[{"name":"Samsung Electronics, San Jose, CA U.S.A."}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2013.2283277"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.89"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"e_1_3_2_1_5_1","volume-title":"Computational RAM: A Memory-SIMD Hybrid and its Application to DSP,\" in IEEE Custom Integrated Circuits Conference (CICC)","author":"Elliott D. G.","year":"1992","unstructured":"D. G. Elliott , W. M. Snelgrove , and M. Stumm , \" Computational RAM: A Memory-SIMD Hybrid and its Application to DSP,\" in IEEE Custom Integrated Circuits Conference (CICC) , 1992 . D. G. Elliott, W. M. Snelgrove, and M. Stumm, \"Computational RAM: A Memory-SIMD Hybrid and its Application to DSP,\" in IEEE Custom Integrated Circuits Conference (CICC), 1992."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750386"},{"key":"e_1_3_2_1_7_1","volume-title":"Chameleon: Versatile and Practical Near-DRAM Acceleration Architecture for Large Memory Systems,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO)","author":"Asghari-Moghaddam H.","year":"2016","unstructured":"H. Asghari-Moghaddam , Y. H. Son , J. Ahn , and N. S. Kim , \" Chameleon: Versatile and Practical Near-DRAM Acceleration Architecture for Large Memory Systems,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO) , 2016 . H. Asghari-Moghaddam, Y. H. Son, J. Ahn, and N. S. Kim, \"Chameleon: Versatile and Practical Near-DRAM Acceleration Architecture for Large Memory Systems,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO), 2016."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.8"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.22"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132434"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541951"},{"key":"e_1_3_2_1_14_1","volume-title":"Application-transparent near-memory processing architecture with memory channel network,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO)","author":"Alian M.","year":"2018","unstructured":"M. Alian , \" Application-transparent near-memory processing architecture with memory channel network,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO) , 2018 . M. Alian et al., \"Application-transparent near-memory processing architecture with memory channel network,\" in ACM\/IEEE International Symposium on Microarchitecture (MICRO), 2018."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.14778\/2994509.2994512"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142548"},{"key":"e_1_3_2_1_18_1","volume-title":"INSIDER: Redesign storage system for emerging high-performance drive,\" SRC\/CRISP presentation","author":"Ruan Z.","year":"2019","unstructured":"Z. Ruan , T.H. and J. Cong . \" INSIDER: Redesign storage system for emerging high-performance drive,\" SRC\/CRISP presentation , 2019 . Z. Ruan, T.H. and J. Cong. \"INSIDER: Redesign storage system for emerging high-performance drive,\" SRC\/CRISP presentation, 2019."}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Las Vegas NV USA","acronym":"DAC '19"},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3323484","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,5]],"date-time":"2023-01-05T22:29:39Z","timestamp":1672957779000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3323484"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":17,"alternative-id":["10.1145\/3316781.3323484","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3323484","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}