{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T09:56:14Z","timestamp":1725789374278},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317872","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":19,"title":["NV-BNN"],"prefix":"10.1145","author":[{"given":"Chih-Cheng","family":"Chang","sequence":"first","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Ming-Hung","family":"Wu","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Jia-Wei","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Chun-Hsien","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Vivek","family":"Parmar","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Heng-Yuan","family":"Lee","sequence":"additional","affiliation":[{"name":"Industrial Technology Research Institute, Chutung, Hsinchu, Taiwan"}]},{"given":"Jeng-Hua","family":"Wei","sequence":"additional","affiliation":[{"name":"Industrial Technology Research Institute, Chutung, Hsinchu, Taiwan"}]},{"given":"Shyh-Shyuan","family":"Sheu","sequence":"additional","affiliation":[{"name":"Industrial Technology Research Institute, Chutung, Hsinchu, Taiwan"}]},{"given":"Manan","family":"Suri","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Delhi, New Delhi, India"}]},{"given":"Tian-Sheuan","family":"Chang","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Tuo-Hung","family":"Hou","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan and Industrial Technology Research Institute, Chutung, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"e_1_3_2_1_2_1","first-page":"64","article-title":"Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures","author":"Eryilmaz S. B.","year":"2015","unstructured":"S. B. Eryilmaz , \" Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures ,\" in IEDM Tech. Dig. , 2015 , pp. 64 -- 67 . S. B. Eryilmaz et al., \"Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures,\" in IEDM Tech. Dig., 2015, pp. 64--67.","journal-title":"IEDM Tech. Dig."},{"volume-title":"Training deep neural networks with binary weights during propagations,\" arXiv:1511.00363","year":"2015","author":"Courbariaux M.","key":"e_1_3_2_1_3_1","unstructured":"M. Courbariaux , Y. Bengio , and J-P David , \"BinaryConnect : Training deep neural networks with binary weights during propagations,\" arXiv:1511.00363 , 2015 . M. Courbariaux, Y. Bengio, and J-P David, \"BinaryConnect: Training deep neural networks with binary weights during propagations,\" arXiv:1511.00363, 2015."},{"volume-title":"XNOR-Net: ImageNet classification using binary convolutional neural networks,\" arXiv:1603.05279","year":"2016","author":"Rastegariy M.","key":"e_1_3_2_1_4_1","unstructured":"M. Rastegariy , V. Ordonezy , J. Redmon , and A. Farhadi , \" XNOR-Net: ImageNet classification using binary convolutional neural networks,\" arXiv:1603.05279 , 2016 . M. Rastegariy, V. Ordonezy, J. Redmon, and A. Farhadi, \"XNOR-Net: ImageNet classification using binary convolutional neural networks,\" arXiv:1603.05279, 2016."},{"key":"e_1_3_2_1_5_1","first-page":"1","article-title":"BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS","author":"Moons B.","year":"2018","unstructured":"B. Moons , D. Bankman , L. Yang , B. Murmann , and M. Verhelst , \" BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS ,\" in Proc. CICC , 2018 , pp. 1 -- 4 . B. Moons, D. Bankman, L. Yang, B. Murmann, and M. Verhelst, \"BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS,\" in Proc. CICC, 2018, pp. 1--4.","journal-title":"Proc."},{"key":"e_1_3_2_1_6_1","first-page":"173","article-title":"XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks","author":"Jiang Z.","year":"2018","unstructured":"Z. Jiang , S. Yin , M. Seok , and J.-S. Seo , \" XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks ,\" in Proc. VLSI Tech. , 2018 , pp. 173 -- 174 . Z. Jiang, S. Yin, M. Seok, and J.-S. Seo, \"XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks,\" in Proc. VLSI Tech., 2018, pp. 173--174.","journal-title":"Proc. VLSI Tech."},{"key":"e_1_3_2_1_7_1","first-page":"478","article-title":"An N40 256K\u00d744 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance","author":"Chou C.-C.","year":"2018","unstructured":"C.-C. Chou , \" An N40 256K\u00d744 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance ,\" in ISSCC Tech. Dig. 2018 , pp. 478 -- 479 . C.-C. Chou et al., \"An N40 256K\u00d744 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance,\" in ISSCC Tech. Dig. 2018, pp. 478--479.","journal-title":"ISSCC Tech. Dig."},{"key":"e_1_3_2_1_8_1","first-page":"480","article-title":"A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination","author":"Dong Q.","year":"2018","unstructured":"Q. Dong , \" A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination ,\" in ISSCC Tech. Dig. 2018 , pp. 480 -- 481 . Q. Dong et al., \"A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination,\" in ISSCC Tech. Dig. 2018, pp. 480--481.","journal-title":"ISSCC Tech. Dig."},{"key":"e_1_3_2_1_9_1","first-page":"663","article-title":"Highly functional and reliable 8Mb STT-MRAM embedded in 28nm Logic","author":"Song Y. J.","year":"2016","unstructured":"Y. J. Song , \" Highly functional and reliable 8Mb STT-MRAM embedded in 28nm Logic ,\" in IEDM Tech. Dig. , 2016 , pp. 663 -- 666 . Y. J. Song et al., \"Highly functional and reliable 8Mb STT-MRAM embedded in 28nm Logic,\" in IEDM Tech. Dig., 2016, pp. 663--666.","journal-title":"IEDM Tech. Dig."},{"key":"e_1_3_2_1_10_1","first-page":"208","article-title":"CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications","author":"Shum D.","year":"2017","unstructured":"D. Shum , \" CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications ,\" in Proc. VLSI Tech. , 2017 , pp. 208 -- 209 . D. Shum et al., \"CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications,\" in Proc. VLSI Tech., 2017, pp. 208--209.","journal-title":"Proc. VLSI Tech."},{"key":"e_1_3_2_1_11_1","first-page":"65","article-title":"Demonstration of ultra-low voltage and ultra low power STT-MRAM designed for compatibility with 0x node embedded LLC applications","author":"Jan G.","year":"2018","unstructured":"G. Jan , \" Demonstration of ultra-low voltage and ultra low power STT-MRAM designed for compatibility with 0x node embedded LLC applications ,\" in Proc. VLSI Tech. , 2018 , pp. 65 -- 66 . G. Jan et al., \"Demonstration of ultra-low voltage and ultra low power STT-MRAM designed for compatibility with 0x node embedded LLC applications,\" in Proc. VLSI Tech., 2018, pp. 65--66.","journal-title":"Proc. VLSI Tech."},{"key":"e_1_3_2_1_12_1","first-page":"278","article-title":"Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network","author":"Chang C.-C.","year":"2017","unstructured":"C.-C. Chang , , \" Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network ,\" in IEDM Tech. Dig. , 2017 , pp. 278 -- 281 . C.-C. Chang, et al., \"Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network,\" in IEDM Tech. Dig., 2017, pp. 278--281.","journal-title":"IEDM Tech. Dig."},{"key":"e_1_3_2_1_13_1","first-page":"697","article-title":"Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element","author":"Burr G. W.","year":"2014","unstructured":"G. W. Burr , \" Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element ,\" in IEDM Tech. Dig. , 2014 , pp. 697 -- 700 . G. W. Burr et al., \"Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element,\" in IEDM Tech. Dig., 2014, pp. 697--700.","journal-title":"IEDM Tech. Dig."},{"key":"e_1_3_2_1_14_1","first-page":"194","volume-title":"ICCAD","author":"Chen P.-Y.","year":"2015","unstructured":"P.-Y. Chen effects of non-ideal synaptic device characteristics for on-chip learning,\" in Proc . ICCAD 2015 , pp. 194 -- 199 . P.-Y. Chen et al., \"Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,\" in Proc. ICCAD 2015, pp. 194--199."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2017.2771529"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2015.2414423"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2324560"},{"key":"e_1_3_2_1_18_1","first-page":"30","volume-title":"IMW","author":"Fantini A.","year":"2013","unstructured":"A. Fantini switching variability in HfO2 RRAM,\" in Proc . IMW 2013 , pp. 30 -- 33 . A. Fantini et al., \"Intrinsic switching variability in HfO2 RRAM,\" in Proc. IMW 2013, pp. 30--33."},{"key":"e_1_3_2_1_19_1","first-page":"1","volume-title":"Proc. NIPS","author":"Paszke A.","year":"2017","unstructured":"A. Paszke in Proc. NIPS 2017 , pp. 1 -- 4 . A. Paszke et al., \"Automatic differentiation in PyTorch,\" in Proc. NIPS 2017, pp. 1--4."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/23\/7\/075201"}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Las Vegas NV USA","acronym":"DAC '19"},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317872","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T03:30:32Z","timestamp":1672975832000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317872"}},"subtitle":["An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge"],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":20,"alternative-id":["10.1145\/3316781.3317872","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317872","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}