乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T00:54:39Z","timestamp":1740099279483,"version":"3.37.3"},"publisher-location":"New York, NY, USA","reference-count":30,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,6,2]],"date-time":"2020-06-02T00:00:00Z","timestamp":1591056000000},"content-version":"vor","delay-in-days":366,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1813370"],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317851","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore Computing"],"prefix":"10.1145","author":[{"given":"Venkata Yaswanth","family":"Raparti","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering Colorado State University, Fort Collins, CO, U.S.A."}]},{"given":"Sudeep","family":"Pasricha","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering Colorado State University, Fort Collins, CO, U.S.A."}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"4","article-title":"RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures","volume":"4","author":"Pasricha S.","year":"2018","unstructured":"V.Y.Raparti, S. Pasricha \" RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures \" IEEE Transactions on Multi-Scale Computing Systems , vol: 4 , no: 4 , pp. 874--887, Oct-Dec 2018 . V.Y.Raparti, S. Pasricha \"RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures\" IEEE Transactions on Multi-Scale Computing Systems, vol: 4, no: 4, pp. 874--887, Oct-Dec 2018.","journal-title":"IEEE Transactions on Multi-Scale Computing Systems"},{"key":"e_1_3_2_1_2_1","volume-title":"IEEE\/ACM NOCS","author":"S.","year":"2018","unstructured":"V.Y.Raparti, S. Pasricha \"DAPPER : Data Aware Approximate NoC for GPGPU Architectures.\" Proc . IEEE\/ACM NOCS 2018 . V.Y.Raparti, S. Pasricha \"DAPPER: Data Aware Approximate NoC for GPGPU Architectures.\" Proc. IEEE\/ACM NOCS 2018."},{"key":"e_1_3_2_1_3_1","unstructured":"Arteris http:\/\/www.arteris.com\/ Arteris http:\/\/www.arteris.com\/"},{"key":"e_1_3_2_1_4_1","volume-title":"Low Noise, L3 Cache Side-Channel Attack.\" Proc. USENIX Security Sym.","author":"Yarom Y.","year":"2014","unstructured":"Y. Yarom , \" FLUSH+ RELOAD: A High Resolution , Low Noise, L3 Cache Side-Channel Attack.\" Proc. USENIX Security Sym. 2014 . Y. Yarom et al., \"FLUSH+ RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack.\" Proc. USENIX Security Sym. 2014."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE HOST","author":"Akkaya E.C.","year":"2018","unstructured":"N. E.C. Akkaya , chip odometers using intentional controlled aging.\" Proc . IEEE HOST 2018 . N.E.C. Akkaya, et al. \"Secure chip odometers using intentional controlled aging.\" Proc. IEEE HOST 2018."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.35"},{"key":"e_1_3_2_1_8_1","volume-title":"End-to-end error correction and online diagnosis for on-chip networks.\" Proc. of the International Test Conference (ITC)","author":"Shamshiri S.","year":"2011","unstructured":"S. Shamshiri , \" End-to-end error correction and online diagnosis for on-chip networks.\" Proc. of the International Test Conference (ITC) , 2011 . S. Shamshiri, et al. \"End-to-end error correction and online diagnosis for on-chip networks.\" Proc. of the International Test Conference (ITC), 2011."},{"key":"e_1_3_2_1_9_1","volume-title":"Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","author":"Manoj Kumar JYV","year":"2018","unstructured":"JYV Manoj Kumar , Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , 2018 . JYV Manoj Kumar, et al. \"Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip.\" Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018."},{"key":"e_1_3_2_1_10_1","volume-title":"Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs.\" Proc","author":"Sep\u00falveda J.","year":"2015","unstructured":"J. Sep\u00falveda , \" Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs.\" Proc . IEEE ReCoSoC , 2015 . J. Sep\u00falveda, et al. \"Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs.\" Proc. IEEE ReCoSoC, 2015."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593144"},{"key":"e_1_3_2_1_12_1","volume-title":"Packet security with path sensitization for NoCs.\" Proc","author":"Boraten T.","year":"2016","unstructured":"T. Boraten , \" Packet security with path sensitization for NoCs.\" Proc . IEEE DATE , 2016 . T. Boraten, et al. \"Packet security with path sensitization for NoCs.\" Proc. IEEE DATE, 2016."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485972"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196118"},{"key":"e_1_3_2_1_15_1","volume-title":"Springer Berlin\/Heidelberg","author":"Skorobogatov S.","year":"2011","unstructured":"S. Skorobogatov , \"Physical attacks and tamper resistance,\" in Introduction to Hardware Security and Trust , Springer Berlin\/Heidelberg , 2011 . S. Skorobogatov, \"Physical attacks and tamper resistance,\" in Introduction to Hardware Security and Trust, Springer Berlin\/Heidelberg, 2011."},{"key":"e_1_3_2_1_16_1","volume-title":"International Test Conf. (ITC)","author":"Dubrova E.","year":"2014","unstructured":"E. Dubrova , LBIST for feedback shift register-based cryptographic systems,\" Proc . International Test Conf. (ITC) , 2014 . E. Dubrova, et al. \"Secure and efficient LBIST for feedback shift register-based cryptographic systems,\" Proc. International Test Conf. (ITC), 2014."},{"key":"e_1_3_2_1_17_1","volume-title":"Differential power analysis.\" Springer- Verlag","author":"Kocher P.","year":"1999","unstructured":"P. Kocher , , \" Differential power analysis.\" Springer- Verlag , 1999 . P. Kocher, et al., \"Differential power analysis.\" Springer- Verlag, 1999."},{"key":"e_1_3_2_1_18_1","volume-title":"IEEE International Symposium on System-on-Chip (SoC)","author":"Dubrova E.","year":"2014","unstructured":"E. Dubrova , BIST for Trojan detection in SoC.\" Proc . IEEE International Symposium on System-on-Chip (SoC) , 2014 E. Dubrova, et al. \"Keyed logic BIST for Trojan detection in SoC.\" Proc. IEEE International Symposium on System-on-Chip (SoC), 2014"},{"key":"e_1_3_2_1_19_1","volume-title":"IEEE ISQED","author":"Oya M.","year":"2016","unstructured":"M. Oya , \"In-situ Trojan authentication for invalidating hardware-Trojan functions.\" Proc . IEEE ISQED , 2016 . M. Oya, \"In-situ Trojan authentication for invalidating hardware-Trojan functions.\" Proc. IEEE ISQED, 2016."},{"key":"e_1_3_2_1_20_1","volume-title":"EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.\" Proc IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","author":"Hussain M.","year":"2018","unstructured":"M. Hussain , \" EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.\" Proc IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018 . M. Hussain, et al. \"EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip.\" Proc IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2018."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.15"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903032"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.12.013"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145703"},{"key":"e_1_3_2_1_25_1","unstructured":"Vivado HLS tool Xilinx. https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design.html. Vivado HLS tool Xilinx. https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/integration\/esl-design.html."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320885"},{"key":"e_1_3_2_1_29_1","volume-title":"IEEE ASAP","author":"Catania V.","year":"2015","unstructured":"V. Catania , : An open, extensible and cycle-accurate network on chip simulator.\" Proc . IEEE ASAP , 2015 . V. Catania, et al. \"Noxim: An open, extensible and cycle-accurate network on chip simulator.\" Proc. IEEE ASAP, 2015."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921258"},{"key":"e_1_3_2_1_31_1","unstructured":"Cadence https:\/\/www.cadence.com\/content\/cadence-www\/tools\/customic-analog-rf-design\/layout-design\/virtuoso-layout-suite.html Cadence https:\/\/www.cadence.com\/content\/cadence-www\/tools\/customic-analog-rf-design\/layout-design\/virtuoso-layout-suite.html"}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Las Vegas NV USA","acronym":"DAC '19"},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317851","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317851","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T03:32:57Z","timestamp":1672975977000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317851"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":30,"alternative-id":["10.1145\/3316781.3317851","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317851","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}