乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,30]],"date-time":"2024-12-30T18:46:39Z","timestamp":1735584399758},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2019,6,2]],"date-time":"2019-06-02T00:00:00Z","timestamp":1559433600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317829","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":128,"title":["FPGA\/DNN Co-Design"],"prefix":"10.1145","author":[{"given":"Cong","family":"Hao","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Xiaofan","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Yuhong","family":"Li","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Sitao","family":"Huang","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Jinjun","family":"Xiong","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center"}]},{"given":"Kyle","family":"Rupnow","sequence":"additional","affiliation":[{"name":"Inspirit IoT, Inc."}]},{"given":"Wen-mei","family":"Hwu","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign and Inspirit IoT, Inc."}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"e_1_3_2_1_3_1","volume-title":"FPL","author":"Xiaofan","year":"2017","unstructured":"Xiaofan Zhang et al. High-performance video content recognition with long-term recurrent convolutional network for FPGA . In FPL , 2017 . Xiaofan Zhang et al. High-performance video content recognition with long-term recurrent convolutional network for FPGA. In FPL, 2017."},{"key":"e_1_3_2_1_4_1","volume-title":"FPL","author":"Junsong","year":"2018","unstructured":"Junsong Wang et al. Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA . In FPL , 2018 . Junsong Wang et al. Design flow of accelerating hybrid extremely low bit-width neural network in embedded FPGA. In FPL, 2018."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287717"},{"key":"e_1_3_2_1_7_1","volume-title":"ICCAD","author":"Xiaofan","year":"2017","unstructured":"Xiaofan Zhang et al. Machine learning on FPGAs to face the IoT revolution . In ICCAD , 2017 . Xiaofan Zhang et al. Machine learning on FPGAs to face the IoT revolution. In ICCAD, 2017."},{"key":"e_1_3_2_1_8_1","volume-title":"Learning transferable architectures for scalable image recognition. arXiv:1707.07012","author":"Barret Zoph","year":"2017","unstructured":"Barret Zoph et al. Learning transferable architectures for scalable image recognition. arXiv:1707.07012 , 2017 . Barret Zoph et al. Learning transferable architectures for scalable image recognition. arXiv:1707.07012, 2017."},{"key":"e_1_3_2_1_9_1","volume-title":"Neural architecture search with reinforcement learning. arXiv:1611.01578","author":"Zoph Barret","year":"2016","unstructured":"Barret Zoph and Quoc V Le . Neural architecture search with reinforcement learning. arXiv:1611.01578 , 2016 . Barret Zoph and Quoc V Le. Neural architecture search with reinforcement learning. arXiv:1611.01578, 2016."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2013353"},{"key":"e_1_3_2_1_11_1","volume-title":"FPT","author":"Kyle","year":"2011","unstructured":"Kyle Rupnow et al. High level synthesis of stereo matching: Productivity, performance, and software constraints . In FPT , 2011 . Kyle Rupnow et al. High level synthesis of stereo matching: Productivity, performance, and software constraints. In FPT, 2011."},{"key":"e_1_3_2_1_12_1","volume-title":"Regularized evolution for image classifier architecture search. arXiv:1802.01548","author":"Esteban Real","year":"2018","unstructured":"Esteban Real et al. Regularized evolution for image classifier architecture search. arXiv:1802.01548 , 2018 . Esteban Real et al. Regularized evolution for image classifier architecture search. arXiv:1802.01548, 2018."},{"key":"e_1_3_2_1_13_1","volume-title":"Mnasnet: Platform-aware neural architecture search for mobile. arXiv:1807.11626","author":"Mingxing Tan","year":"2018","unstructured":"Mingxing Tan et al. Mnasnet: Platform-aware neural architecture search for mobile. arXiv:1807.11626 , 2018 . Mingxing Tan et al. Mnasnet: Platform-aware neural architecture search for mobile. arXiv:1807.11626, 2018."},{"key":"e_1_3_2_1_14_1","volume-title":"Proxylessnas: Direct neural architecture search on target task and hardware. arXiv:1812.00332","author":"Han Cai","year":"2018","unstructured":"Han Cai et al. Proxylessnas: Direct neural architecture search on target task and hardware. arXiv:1812.00332 , 2018 . Han Cai et al. Proxylessnas: Direct neural architecture search on target task and hardware. arXiv:1812.00332, 2018."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021745"},{"key":"e_1_3_2_1_16_1","volume-title":"ASP-DAC","author":"Mohammad","year":"2016","unstructured":"Mohammad Motamedi et al. Design space exploration of FPGA-based deep convolutional neural networks . In ASP-DAC , 2016 . Mohammad Motamedi et al. Design space exploration of FPGA-based deep convolutional neural networks. In ASP-DAC, 2016."},{"key":"e_1_3_2_1_17_1","volume-title":"DATE","author":"Guanwen","year":"2017","unstructured":"Guanwen Zhong et al. Design space exploration of FPGA-based accelerators with multi-level parallelism . In DATE , 2017 . Guanwen Zhong et al. Design space exploration of FPGA-based accelerators with multi-level parallelism. In DATE, 2017."},{"key":"e_1_3_2_1_18_1","volume-title":"CVPR","author":"Kaiming","year":"2016","unstructured":"Kaiming He et al. Deep residual learning for image recognition . In CVPR , 2016 . Kaiming He et al. Deep residual learning for image recognition. In CVPR, 2016."},{"key":"e_1_3_2_1_19_1","volume-title":"CVPR","author":"Mark","year":"2018","unstructured":"Mark Sandler et al. Mobilenetv2: Inverted residuals and linear bottlenecks . In CVPR , 2018 . Mark Sandler et al. Mobilenetv2: Inverted residuals and linear bottlenecks. In CVPR, 2018."},{"key":"e_1_3_2_1_20_1","unstructured":"2018 DAC System Design Contest. http:\/\/www.cse.cuhk.edu.hk\/~byu\/2018-DAC-HDC\/ranking.html#may. Accessed: 2018-09-04. 2018 DAC System Design Contest. http:\/\/www.cse.cuhk.edu.hk\/~byu\/2018-DAC-HDC\/ranking.html#may. Accessed: 2018-09-04."},{"key":"e_1_3_2_1_21_1","volume-title":"DAC-SDC low power object detection challenge for UAV applications. arXiv:1809.00110","author":"Xiaowei Xu","year":"2018","unstructured":"Xiaowei Xu et al. DAC-SDC low power object detection challenge for UAV applications. arXiv:1809.00110 , 2018 . Xiaowei Xu et al. DAC-SDC low power object detection challenge for UAV applications. arXiv:1809.00110, 2018."},{"key":"e_1_3_2_1_22_1","unstructured":"1st Place in FPGA Category. https:\/\/github.com\/hirayaku\/DAC2018-TGIIF. Accessed: 2018-10-01. 1st Place in FPGA Category. https:\/\/github.com\/hirayaku\/DAC2018-TGIIF. Accessed: 2018-10-01."}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","location":"Las Vegas NV USA","acronym":"DAC '19","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317829","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T03:52:38Z","timestamp":1672977158000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317829"}},"subtitle":["An Efficient Design Methodology for IoT Intelligence on the Edge"],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":22,"alternative-id":["10.1145\/3316781.3317829","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317829","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}