{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T20:44:56Z","timestamp":1730321096956,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2020,6,2]],"date-time":"2020-06-02T00:00:00Z","timestamp":1591056000000},"content-version":"vor","delay-in-days":366,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1755874"],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2019,6,2]]},"DOI":"10.1145\/3316781.3317819","type":"proceedings-article","created":{"date-parts":[[2019,5,23]],"date-time":"2019-05-23T18:07:13Z","timestamp":1558634833000},"page":"1-6","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["STFL"],"prefix":"10.1145","author":[{"given":"Payman","family":"Behnam","sequence":"first","affiliation":[{"name":"University of Utah"}]},{"given":"Mahdi Nazm","family":"Bojnordi","sequence":"additional","affiliation":[{"name":"University of Utah"}]}],"member":"320","published-online":{"date-parts":[[2019,6,2]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810061"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015395"},{"first-page":"320","volume-title":"Cafo: Cost aware flip optimization for asymmetric memories,\" in International Symposium on High Performance Computer Architecture (HPCA)","year":"2015","author":"Maddah R.","key":"e_1_3_2_1_5_1"},{"key":"e_1_3_2_1_6_1","first-page":"6","article-title":"Limited-weight codes for low-power i\/o","volume":"6","author":"Stan M. R.","year":"1994","journal-title":"International Workshop on Low Power Design"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357133"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.68"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540729"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3149412.3149417"},{"first-page":"59","volume-title":"Non-uniform power access in large caches with low-swing wires,\" in International Conference on High Performance Computing (HiPC)","year":"2009","author":"Udipi A. N.","key":"e_1_3_2_1_11_1"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.210023"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/280756.280876"},{"key":"e_1_3_2_1_14_1","unstructured":"\"Free PDK 45nm open-access based PDK for the 45nm technology node.\" http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK. \"Free PDK 45nm open-access based PDK for the 45nm technology node.\" http:\/\/www.eda.ncsu.edu\/wiki\/FreePDK."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.91"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.845893"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2018.05.037"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522340"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125925"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.223990"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306783"},{"key":"e_1_3_2_1_23_1","first-page":"22","article-title":"Cacti 6.0: A tool to model large caches","author":"Muralimanohar N.","year":"2009","journal-title":"HP Laboratories"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4471-4492-2_8"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250708"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531542.1531557"},{"key":"e_1_3_2_1_27_1","unstructured":"\"Products formerly skylake.\" https:\/\/ark.intel.com\/products\/codename\/37572\/Skylake. \"Products formerly skylake.\" https:\/\/ark.intel.com\/products\/codename\/37572\/Skylake."},{"key":"e_1_3_2_1_28_1","unstructured":"T. A. Dye \"Memory controller including compression\/decompression capabilities for improved data access \" Apr. 9 2002. US Patent 6 370 631. T. A. Dye \"Memory controller including compression\/decompression capabilities for improved data access \" Apr. 9 2002. US Patent 6 370 631."},{"first-page":"638","volume-title":"Memzip: Exploring unconventional benefits from memory compression,\" in IEEE International Symposium on High Performance Computer Architecture (HPCA)","year":"2014","author":"Shafiee A.","key":"e_1_3_2_1_29_1"}],"event":{"name":"DAC '19: The 56th Annual Design Automation Conference 2019","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-CEDA","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Las Vegas NV USA","acronym":"DAC '19"},"container-title":["Proceedings of the 56th Annual Design Automation Conference 2019"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317819","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3316781.3317819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,6]],"date-time":"2023-01-06T03:31:54Z","timestamp":1672975914000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3316781.3317819"}},"subtitle":["Energy-Efficient Data Movement with Slow Transition Fast Level Signaling"],"short-title":[],"issued":{"date-parts":[[2019,6,2]]},"references-count":29,"alternative-id":["10.1145\/3316781.3317819","10.1145\/3316781"],"URL":"https:\/\/doi.org\/10.1145\/3316781.3317819","relation":{},"subject":[],"published":{"date-parts":[[2019,6,2]]},"assertion":[{"value":"2019-06-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}