乐胖代购免代理版

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Code Optim."],"published-print":{"date-parts":[[2019,3,31]]},"abstract":"Single instruction multiple data (SIMD) has been adopted for decades because of its superior performance and power efficiency. The SIMD capability (i.e., width, number of registers, and advanced instructions) has diverged rapidly on different SIMD instruction-set architectures (ISAs). Therefore, migrating existing applications to another host ISA that has fewer but longer SIMD registers and more advanced instructions raises the issues of asymmetric SIMD capability. To date, this issue has been overlooked and the host SIMD capability is underutilized, resulting in suboptimal performance. In this article, we present a novel binary translation technique called spill-aware superword level parallelism (saSLP), which combines short ARMv8 instructions and registers in the guest binaries to exploit the x86 AVX2 host\u2019s parallelism, register capacity, and gather instructions. Our experiment results show that saSLP improves the performance by 1.6\u00d7 (2.3\u00d7) across a number of benchmarks and reduces spilling by 97% (99%) for ARMv8 to x86 AVX2 (AVX-512) translation. Furthermore, with AVX2 (AVX-512) gather instructions, saSLP speeds up several data-irregular applications that cannot be vectorized on ARMv8 NEON by up to 3.9\u00d7 (4.2\u00d7).<\/jats:p>","DOI":"10.1145\/3301488","type":"journal-article","created":{"date-parts":[[2019,2,14]],"date-time":"2019-02-14T19:36:17Z","timestamp":1550172977000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Exploiting SIMD Asymmetry in ARM-to-x86 Dynamic Binary Translation"],"prefix":"10.1145","volume":"16","author":[{"given":"Yu-Ping","family":"Liu","sequence":"first","affiliation":[{"name":"National Taiwan University, Daan Dist. Taipei, Taiwan"}]},{"given":"Ding-Yong","family":"Hong","sequence":"additional","affiliation":[{"name":"Academia Sinica, Nankang Dist. Taipei, Taiwan"}]},{"given":"Jan-Jan","family":"Wu","sequence":"additional","affiliation":[{"name":"Academia Sinica, Nankang Dist. Taipei, Taiwan"}]},{"given":"Sheng-Yu","family":"Fu","sequence":"additional","affiliation":[{"name":"National Taiwan University, Daan Dist. Taipei, Taiwan"}]},{"given":"Wei-Chung","family":"Hsu","sequence":"additional","affiliation":[{"name":"National Taiwan University, Daan Dist. Taipei, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2019,2,13]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM Ltd. 2015. ARM Cortex-A Series Programmer\u2019s Guide for ARMv8-A. ARM Ltd. 2015. ARM Cortex-A Series Programmer\u2019s Guide for ARMv8-A."},{"key":"e_1_2_1_2_1","unstructured":"ARM Ltd. 2017. ARM Architecture Reference Manual Supplement: The Scalable Vector Extension (SVE) for ARMv8-A. ARM Ltd. 2017. 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