乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:33:12Z","timestamp":1725809592485},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T00:00:00Z","timestamp":1525737600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,5,8]]},"DOI":"10.1145\/3203217.3203235","type":"proceedings-article","created":{"date-parts":[[2018,7,26]],"date-time":"2018-07-26T07:58:06Z","timestamp":1532591886000},"page":"121-128","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["CMH"],"prefix":"10.1145","author":[{"given":"Cheng","family":"Qian","sequence":"first","affiliation":[{"name":"National University of Defense Technology, ChangSha, China"}]},{"given":"Libo","family":"Huang","sequence":"additional","affiliation":[{"name":"National University of Defense Technology, ChangSha, China"}]},{"given":"Qi","family":"Yu","sequence":"additional","affiliation":[{"name":"National University of Defense Technology, ChangSha, China"}]},{"given":"Zhiying","family":"Wang","sequence":"additional","affiliation":[{"name":"National University of Defense Technology, ChangSha, China"}]},{"given":"Bruce","family":"Childers","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}]}],"member":"320","published-online":{"date-parts":[[2018,5,8]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"{n. d.}. Hybrid memory cube specification 2.1. ({n. d.}). https:\/\/www.hybridmemorycube.org {n. d.}. Hybrid memory cube specification 2.1. ({n. d.}). https:\/\/www.hybridmemorycube.org"},{"key":"e_1_3_2_1_2_1","unstructured":"{n. d.}. internal technology roadmap for semiconductors 2.0. ({n. d.}). https:\/\/www.semiconductors.org\/ {n. d.}. internal technology roadmap for semiconductors 2.0. ({n. d.}). https:\/\/www.semiconductors.org\/"},{"key":"e_1_3_2_1_3_1","unstructured":"{n. d.}. JEDEC specifications (Wide I\/O HBM). ({n. d.}). https:\/\/www.jedec.org {n. d.}. JEDEC specifications (Wide I\/O HBM). ({n. d.}). https:\/\/www.jedec.org"},{"key":"e_1_3_2_1_4_1","unstructured":"{n. d.}. Technology Roadmap of DRAM for Three Major manufacturers: Samsung SK-Hynix and Micron. ({n. d.}). https:\/\/www.techinsights.com\/ {n. d.}. Technology Roadmap of DRAM for Three Major manufacturers: Samsung SK-Hynix and Micron. ({n. d.}). https:\/\/www.techinsights.com\/"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2663761.2663764"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337204"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2770287.2770300"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062811"},{"key":"e_1_3_2_1_13_1","unstructured":"Fred Douglis. 1993. The Compression Cache: Using On-line Compression to Extend Physical Memory.. In USENIX Winter. Citeseer 519--529. Fred Douglis. 1993. The Compression Cache: Using On-line Compression to Extend Physical Memory.. In USENIX Winter . Citeseer 519--529."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400714"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1069978"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346190"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1952.273898"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2600601"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657041"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.12"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.62"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1064978.1065034"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2435788"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818982"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2013.6673280"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370870"},{"key":"e_1_3_2_1_28_1","volume-title":"Five emerging DRAM interfaces you should know for your next design. Cadence Design Systems","author":"Raghavan Gopal","year":"2013","unstructured":"Gopal Raghavan . 2013. Five emerging DRAM interfaces you should know for your next design. Cadence Design Systems ( 2013 ). Gopal Raghavan. 2013. Five emerging DRAM interfaces you should know for your next design. Cadence Design Systems (2013)."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.452.0271"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837308"}],"event":{"name":"CF '18: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Ischia Italy","acronym":"CF '18"},"container-title":["Proceedings of the 15th ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3203217.3203235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T17:38:42Z","timestamp":1673458722000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3203217.3203235"}},"subtitle":["compression management for improving capacity in the hybrid memory cube"],"short-title":[],"issued":{"date-parts":[[2018,5,8]]},"references-count":31,"alternative-id":["10.1145\/3203217.3203235","10.1145\/3203217"],"URL":"https:\/\/doi.org\/10.1145\/3203217.3203235","relation":{},"subject":[],"published":{"date-parts":[[2018,5,8]]},"assertion":[{"value":"2018-05-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}