{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T02:06:24Z","timestamp":1725761184155},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2018,5,8]],"date-time":"2018-05-08T00:00:00Z","timestamp":1525737600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"US National Science Foundation","award":["CNS-1643351"]},{"name":"Intel","award":["Intel Strategic Research Alliance Funding"]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2018,5,8]]},"DOI":"10.1145\/3203217.3203233","type":"proceedings-article","created":{"date-parts":[[2018,7,26]],"date-time":"2018-07-26T11:58:06Z","timestamp":1532606286000},"page":"69-77","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["An FPGA framework for edge-centric graph processing"],"prefix":"10.1145","author":[{"given":"Shijie","family":"Zhou","sequence":"first","affiliation":[{"name":"University of Southern California"}]},{"given":"Rajgopal","family":"Kannan","sequence":"additional","affiliation":[{"name":"US Army Research Lab"}]},{"given":"Hanqing","family":"Zeng","sequence":"additional","affiliation":[{"name":"University of Southern California"}]},{"given":"Viktor K.","family":"Prasanna","sequence":"additional","affiliation":[{"name":"University of Southern California"}]}],"member":"320","published-online":{"date-parts":[[2018,5,8]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807184"},{"key":"e_1_3_2_1_2_1","first-page":"31","volume-title":"USENIX Symposium on Operating Systems Design and Implementation (OSDI)","author":"Kyrola A.","year":"2012"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522740"},{"volume-title":"USENIX Symposium on Operating Systems Design and Implementation (OSDI)","year":"2016","author":"Gonzalez J. E.","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Y. Chi G. Dai Y. Wang G. Sun G. Li and H. Yang \"NXgraph: An Efficient Graph Processing System on a Single Machine \" in Proc. of International Conference on Data Engineering (ICDE) pp.409--420 2016. Y. Chi G. Dai Y. Wang G. Sun G. Li and H. Yang \"NXgraph: An Efficient Graph Processing System on a Single Machine \" in Proc. of International Conference on Data Engineering (ICDE) pp.409--420 2016.","DOI":"10.1109\/ICDE.2016.7498258"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.14778\/2809974.2809983"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"crossref","unstructured":"T. Ham L. Wu N. Sundaram N. Satish and Margaret Martonosi \"Graphicionado: A High-performance and Energy-efficient Accelerator for Graph Analytics \" in Proc. of International Symposium on Microarchitecture (MICRO) pp. 1--13 2016. T. Ham L. Wu N. Sundaram N. Satish and Margaret Martonosi \"Graphicionado: A High-performance and Energy-efficient Accelerator for Graph Analytics \" in Proc. of International Symposium on Microarchitecture (MICRO) pp. 1--13 2016.","DOI":"10.1109\/MICRO.2016.7783759"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"crossref","unstructured":"S. Zhou C. Chelmis and V. K. Prasanna \"High-throughput and Energy-efficient Graph Processing on FPGA \" in Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM) pp. 103--110 2016. S. Zhou C. Chelmis and V. K. Prasanna \"High-throughput and Energy-efficient Graph Processing on FPGA \" in Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM) pp. 103--110 2016.","DOI":"10.1109\/FCCM.2016.35"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847339"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380769"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2015.130"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"J. Fowers K. Ovtcharov K. Strauss E. S. Chung and G. Stitt \"A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication \" in Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM) pp. 36--43 2014. J. Fowers K. Ovtcharov K. Strauss E. S. Chung and G. Stitt \"A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication \" in Proc. of International Symposium on Field-Programmable Custom Computing Machines (FCCM) pp. 36--43 2014.","DOI":"10.1109\/FCCM.2014.23"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2019583.2019584"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"S. Zhou C. Chelmis and V. K. Prasanna \"Optimizing Memory Performance for FPGA Implementation of PageRank \" in Proc. of International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2015. S. Zhou C. Chelmis and V. K. Prasanna \"Optimizing Memory Performance for FPGA Implementation of PageRank \" in Proc. of International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2015.","DOI":"10.1109\/ReConFig.2015.7393332"},{"volume-title":"Proc. of Field Programmable Logic and Applications (FPL)","year":"2016","author":"Giefers H.","key":"e_1_3_2_1_15_1"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021737"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2012.30"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2014.30"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174245"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174260"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"E. Nurvitadhi G. Weisz Y. Wang S. Hurkat M. Nguyen J. C. Hoe J. F. Martinez and C. Guestrin \"GraphGen: An FPGA Framework for Vertex-Centric Graph Computation \" in Proc. of Field-Programmable Custom Computing Machines (FCCM) pp. 25--28 2014. E. Nurvitadhi G. Weisz Y. Wang S. Hurkat M. Nguyen J. C. Hoe J. F. Martinez and C. Guestrin \"GraphGen: An FPGA Framework for Vertex-Centric Graph Computation \" in Proc. of Field-Programmable Custom Computing Machines (FCCM) pp. 25--28 2014.","DOI":"10.1109\/FCCM.2014.15"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021739"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847337"},{"volume-title":"Proc. of IEEE High Performance Extreme Computing Conference (HPEC)","year":"2014","author":"Kuppannagari S.","key":"e_1_3_2_1_24_1"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"A. Putnam A. Caulfield E. Chung D. Chiou K. Constantinides J. Demme H. Esmaeilzadeh J. Fowers J. Gray M. Haselman S. Hauck S. Heil A. Hormati J. Kim S. Lanka E. Peterson A. Smith J. Thong P. Xiao D. Burger J. Larus G. Gopal and S. Pope \"A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services \" in Proc. of International Symposium on Computer Architecture (ISCA) 2014. A. Putnam A. Caulfield E. Chung D. Chiou K. Constantinides J. Demme H. Esmaeilzadeh J. Fowers J. Gray M. Haselman S. Hauck S. Heil A. Hormati J. Kim S. Lanka E. Peterson A. Smith J. Thong P. Xiao D. Burger J. Larus G. Gopal and S. Pope \"A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services \" in Proc. of International Symposium on Computer Architecture (ISCA) 2014.","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"e_1_3_2_1_26_1","unstructured":"\"Virtex UltraScale+ FPGA Data Sheet \" https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds923-virtex-ultrascale-plus.pdf \"Virtex UltraScale+ FPGA Data Sheet \" https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds923-virtex-ultrascale-plus.pdf"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-70550-5_17"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.50"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1772690.1772756"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"J. Leskovec K. Lang A. Dasgupta and M. Mahoney \"Community Structure in Large Networks: Natural Cluster Sizes and the Absence of Large Well-Defined Clusters \" in Internet Mathematics 6(1) 2009. J. Leskovec K. Lang A. Dasgupta and M. Mahoney \"Community Structure in Large Networks: Natural Cluster Sizes and the Absence of Large Well-Defined Clusters \" in Internet Mathematics 6(1) 2009.","DOI":"10.1080\/15427951.2009.10129177"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1772690.1772751"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.28"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600227"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851145"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"W. Han D. Mawhirter B. Wu and M. Buland \"Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU \" in Proc. of International Conference on Parallel Architectures and Compilation Techniques (PACT) pp. 233--245 2017. W. Han D. Mawhirter B. Wu and M. Buland \"Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU \" in Proc. of International Conference on Parallel Architectures and Compilation Techniques (PACT) pp. 233--245 2017.","DOI":"10.1109\/PACT.2017.41"},{"key":"e_1_3_2_1_38_1","unstructured":"K. Lakhotia R. Kannan and V. K. Prasanna \"Accelerating PageRank using Partition-Centric Processing \" https:\/\/arxiv.org\/abs\/1709.07122 K. Lakhotia R. Kannan and V. K. Prasanna \"Accelerating PageRank using Partition-Centric Processing \" https:\/\/arxiv.org\/abs\/1709.07122"}],"event":{"name":"CF '18: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Ischia Italy","acronym":"CF '18"},"container-title":["Proceedings of the 15th ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3203217.3203233","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T22:38:13Z","timestamp":1673476693000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3203217.3203233"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,8]]},"references-count":37,"alternative-id":["10.1145\/3203217.3203233","10.1145\/3203217"],"URL":"https:\/\/doi.org\/10.1145\/3203217.3203233","relation":{},"subject":[],"published":{"date-parts":[[2018,5,8]]},"assertion":[{"value":"2018-05-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}