乐胖代购免代理版

{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,9]],"date-time":"2024-07-09T11:14:00Z","timestamp":1720523640087},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2017,11,27]],"date-time":"2017-11-27T00:00:00Z","timestamp":1511740800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2018,3,31]]},"abstract":"Voltage assignment is a well-known technique for circuit design, which has been applied successfully to reduce power consumption in classical 2D integrated circuits (ICs). Its usage in the context of 3D ICs has not been fully explored yet although reducing power in 3D designs is of crucial importance, for example, to tackle the ever-present challenge of thermal management. In this article, we investigate the effective and efficient partitioning of 3D designs into multiple voltage domains during the floorplanning step of physical design. In particular, we introduce, implement, and evaluate novel algorithms for effective integration of voltage assignment into the inner floorplanning loops. Our algorithms are compatible not only with the traditional objectives of 2D floorplanning but also with the additional objectives and constraints of 3D designs, including the planning of through-silicon vias (TSVs) and the thermal management of stacked dies. We test our 3D floorplanner extensively on the GSRC benchmarks as well as on an augmented version of the IBM-HB+ benchmarks. The 3D floorplans are shown to achieve effective trade-offs for power and delays throughout different configurations\u2014our results surpass na\u00efve low-power and high-performance voltage assignment by 17% and 10%, on average. Finally, we release our 3D floorplanning framework as open-source code.<\/jats:p>","DOI":"10.1145\/3149817","type":"journal-article","created":{"date-parts":[[2017,11,28]],"date-time":"2017-11-28T13:21:34Z","timestamp":1511875294000},"page":"1-27","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Multi-Objective 3D Floorplanning with Integrated Voltage Assignment"],"prefix":"10.1145","volume":"23","author":[{"given":"Johann","family":"Knechtel","sequence":"first","affiliation":[{"name":"Masdar Institute, Khalifa University of Science and Technology"}]},{"given":"Jens","family":"Lienig","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Germany"}]},{"given":"Ibrahim (Abe) M.","family":"Elfadel","sequence":"additional","affiliation":[{"name":"Masdar Institute, Khalifa University of Science and Technology, Abu Dhabi, UAE"}]}],"member":"320","published-online":{"date-parts":[[2017,11,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817546"},{"key":"e_1_2_1_2_1","volume-title":"Proc. Int. Symp. Qual. Elec. Des. 189--196","author":"Ahmed M. A.","unstructured":"M. A. Ahmed and M. Chrzanowska-Jeske . 2014. Delay and power optimization with TSV-aware 3D floorplanning . In Proc. Int. Symp. Qual. Elec. Des. 189--196 . M. A. Ahmed and M. Chrzanowska-Jeske. 2014. Delay and power optimization with TSV-aware 3D floorplanning. In Proc. Int. Symp. Qual. Elec. Des. 189--196."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474382"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2544837"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024774"},{"key":"e_1_2_1_6_1","volume-title":"Proc. Des. Autom. Test Europe. 1--6.","author":"Chen H.-T.","unstructured":"H.-T. Chen , H.-L. Lin , Z.-C. Wang , and T. T. Hwang . 2011. A new architecture for power network in 3D IC . In Proc. Des. Autom. Test Europe. 1--6. H.-T. Chen, H.-L. Lin, Z.-C. Wang, and T. T. Hwang. 2011. A new architecture for power network in 3D IC. In Proc. Des. Autom. Test Europe. 1--6."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2014.01.006"},{"key":"e_1_2_1_8_1","volume-title":"GSRC Benchmarks. Retrieved","author":"Dai W.","year":"2017","unstructured":"W. Dai , L. Wu , and S. Zhang . 2000 . GSRC Benchmarks. Retrieved October 21, 2017 from http:\/\/vlsicad.eecs.umich.edu\/BK\/GSRCbench\/ and http:\/\/vlsicad.eecs.umich.edu\/BK\/BlockPacking\/progress.html. W. Dai, L. Wu, and S. Zhang. 2000. GSRC Benchmarks. Retrieved October 21, 2017 from http:\/\/vlsicad.eecs.umich.edu\/BK\/GSRCbench\/ and http:\/\/vlsicad.eecs.umich.edu\/BK\/BlockPacking\/progress.html."},{"key":"e_1_2_1_9_1","volume-title":"Proc. Int. Conf. Comp.-Aided Des. 8--12","author":"Hong X.","year":"2000","unstructured":"X. Hong , G. Huang , Y. Cai , J. Gu , and others. 2000 . Corner block list: An effective and efficient topological representation of non-slicing floorplan . In Proc. Int. Conf. Comp.-Aided Des. 8--12 . X. Hong, G. Huang, Y. Cai, J. Gu, and others. 2000. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proc. Int. Conf. Comp.-Aided Des. 8--12."},{"key":"e_1_2_1_10_1","first-page":"33","article-title":"Thermal and power delivery challenges in 3D ICs. In Three Dimensional Integrated Circuit Design, Y. Xie, J. Cong, and S. S. Sapatnekar (Eds.). Springer, New York, NY","volume":"3","author":"Jain P.","year":"2010","unstructured":"P. Jain , P. Zhou , C. H. Kim , and S. S. Sapatnekar . 2010 . Thermal and power delivery challenges in 3D ICs. In Three Dimensional Integrated Circuit Design, Y. Xie, J. Cong, and S. S. Sapatnekar (Eds.). Springer, New York, NY , Chapter 3 , 33 -- 61 . P. Jain, P. Zhou, C. H. Kim, and S. S. Sapatnekar. 2010. Thermal and power delivery challenges in 3D ICs. In Three Dimensional Integrated Circuit Design, Y. Xie, J. Cong, and S. S. Sapatnekar (Eds.). Springer, New York, NY, Chapter 3, 33--61.","journal-title":"Chapter"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658541"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9591-6"},{"key":"e_1_2_1_13_1","volume-title":"Retrieved","author":"Knechtel J.","year":"2017","unstructured":"J. Knechtel . 2017 . Corblivar Floorplanning Suite and Benchmarks . Retrieved October 21, 2017 from https:\/\/github.com\/IFTE-EDA\/Corblivar. J. Knechtel. 2017. Corblivar Floorplanning Suite and Benchmarks. Retrieved October 21, 2017 from https:\/\/github.com\/IFTE-EDA\/Corblivar."},{"key":"e_1_2_1_14_1","volume-title":"Proc. Int. Symp. Phys. Des. 3--10","author":"Knechtel J.","unstructured":"J. Knechtel and J. Lienig . 2016. Physical design automation for 3D chip stacks -- challenges and solutions . In Proc. Int. Symp. Phys. Des. 3--10 . J. Knechtel and J. Lienig. 2016. Physical design automation for 3D chip stacks -- challenges and solutions. In Proc. Int. Symp. Phys. Des. 3--10."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432141"},{"key":"e_1_2_1_16_1","volume-title":"Proc. Int. Conf. Circ. Sys. Comp. Comm. 267--269","author":"Lee B.","year":"2014","unstructured":"B. Lee , E.-Y. Chung , and H.-J. Lee . 2014 . Voltage islanding technique for concurrent power and temperature optimization in 3D-stacked ICs . In Proc. Int. Conf. Circ. Sys. Comp. Comm. 267--269 . B. Lee, E.-Y. Chung, and H.-J. Lee. 2014. Voltage islanding technique for concurrent power and temperature optimization in 3D-stacked ICs. In Proc. Int. Conf. Circ. Sys. Comp. Comm. 267--269."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514936"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-9542-1"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.6109\/jicce.2014.12.1.046"},{"key":"e_1_2_1_20_1","volume-title":"A Multiple Power Domain Floorplanning in 3D IC. Master\u2019s thesis","author":"Lin H.-L.","year":"2017","unstructured":"H.-L. Lin . 2010. A Multiple Power Domain Floorplanning in 3D IC. Master\u2019s thesis . National Tsing Hua University , Taiwan . Retrieved October 21, 2017 from http:\/\/handle.ncl.edu.tw\/11296\/ndltd\/50629662251624775179. H.-L. Lin. 2010. A Multiple Power Domain Floorplanning in 3D IC. Master\u2019s thesis. National Tsing Hua University, Taiwan. Retrieved October 21, 2017 from http:\/\/handle.ncl.edu.tw\/11296\/ndltd\/50629662251624775179."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2351571"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2131890"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2011.6135430"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2055247"},{"key":"e_1_2_1_25_1","volume-title":"Retrieved","author":"Ng A. N.","year":"2017","unstructured":"A. N. Ng , R. Aggarwal , V. Ramachandran , and I. L. Markov . 2006. IBM-HB+ Benchmarks . Retrieved October 21, 2017 from http:\/\/vlsicad.eecs.umich.edu\/BK\/ISPD06bench\/. A. N. Ng, R. Aggarwal, V. Ramachandran, and I. L. Markov. 2006. IBM-HB+ Benchmarks. Retrieved October 21, 2017 from http:\/\/vlsicad.eecs.umich.edu\/BK\/ISPD06bench\/."},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1115\/InterPACK2009-89072"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464514"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776032"},{"key":"e_1_2_1_29_1","doi-asserted-by":"crossref","unstructured":"J. A. Roy A. N. Ng R. Aggarwal V. Ramachandran and others. 2009. Solving modern mixed-size placement instances. Integration the VLSI Journal 42 2 262--275. J. A. Roy A. N. Ng R. Aggarwal V. Ramachandran and others. 2009. Solving modern mixed-size placement instances. Integration the VLSI Journal 42 2 262--275.","DOI":"10.1016\/j.vlsi.2008.09.003"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2523983"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391511"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2549275"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2650989"},{"key":"e_1_2_1_35_1","volume-title":"Acceleration and Extension. Technical Report","author":"Zhang R.","year":"2017","unstructured":"R. Zhang , M. R. Stan , and K. Skadron . 2015. HotSpot 6.0: Validation , Acceleration and Extension. Technical Report . University of Virginia. Retrieved October 21, 2017 from http:\/\/lava.cs.virginia.edu\/HotSpot\/index.htm. R. Zhang, M. R. Stan, and K. Skadron. 2015. HotSpot 6.0: Validation, Acceleration and Extension. Technical Report. University of Virginia. Retrieved October 21, 2017 from http:\/\/lava.cs.virginia.edu\/HotSpot\/index.htm."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3149817","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,31]],"date-time":"2022-12-31T18:29:14Z","timestamp":1672511354000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3149817"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11,27]]},"references-count":35,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,3,31]]}},"alternative-id":["10.1145\/3149817"],"URL":"https:\/\/doi.org\/10.1145\/3149817","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,11,27]]},"assertion":[{"value":"2007-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-09-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-11-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}