{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,23]],"date-time":"2024-06-23T15:12:04Z","timestamp":1719155524291},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2017,5,25]],"date-time":"2017-05-25T00:00:00Z","timestamp":1495670400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2017,7,31]]},"abstract":"Radiation-induced soft errors have posed an increasing reliability challenge to combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise fast, accurate and scalable soft error rate (SER) estimation methods as part of cost-effective robust circuit design. This paper presents an efficient SER estimation framework for combinational and sequential circuits, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential elements. A novel top-down memoization algorithm is proposed to accelerate the propagation of SETs, and a general schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. The feedback in sequential logic is analyzed with an efficient time frame expansion method. Experimental results on various ISCAS85 combinational benchmark circuits demonstrate that the proposed approach achieves up to 560.2X times speedup with less than 3% difference in terms of SER results compared with the baseline algorithm. The average runtime of the proposed framework on a variety of ISCAS89 benchmark circuits is 7.20s, and the runtime is 119.23s for the largest benchmark circuit with more than 3,000 flip-flops and 17,000 gates.<\/jats:p>","DOI":"10.1145\/3035496","type":"journal-article","created":{"date-parts":[[2017,5,25]],"date-time":"2017-05-25T16:16:45Z","timestamp":1495729005000},"page":"1-21","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":17,"title":["Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits"],"prefix":"10.1145","volume":"22","author":[{"given":"Ji","family":"Li","sequence":"first","affiliation":[{"name":"University of Southern California, Los Angeles, CA"}]},{"given":"Jeffrey","family":"Draper","sequence":"additional","affiliation":[{"name":"Information Sciences Institute and University of Southern California, Marina del Rey, CA"}]}],"member":"320","published-online":{"date-parts":[[2017,5,25]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2691365.2691462"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2006.884788"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2298889"},{"key":"e_1_2_1_4_1","article-title":"An exploration of applying gate-length-biasing techniques to deeply-scaled finfets operating in multiple voltage regimes","author":"Cui Tiansong","year":"2016","journal-title":"IEEE Transactions on Emerging Topics in Computing."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2016.7479211"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2422845"},{"key":"e_1_2_1_7_1","volume-title":"20th Asia and South Pacific Design Automation Conference (ASP-DAC\u201915)","author":"Ebrahimi Mojtaba"},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the 1st 1989 European Test Conference. IEEE, 132--138","author":"Ercolani S."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2013.6604065"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2007.51"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2255624"},{"key":"e_1_2_1_12_1","volume-title":"John Wu, Christian Engelmann, Nathan DeBardeleben, Larry Kaplan, Martin Schulz, and others.","author":"Geist Al","year":"2012"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-015-5517-5"},{"key":"e_1_2_1_14_1","volume-title":"2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC\u201914)","author":"Ryan"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-015-5533-5"},{"key":"e_1_2_1_16_1","volume-title":"Measurement and reporting of alpha particle and terrestrial cosmic rayinduced soft errors in semiconductor devices. JEDEC solid state technology association","author":"JEDEC","year":"2006"},{"key":"e_1_2_1_17_1","volume-title":"Jha and Sandeep Gupta","author":"Niraj","year":"2003"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593196"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2318326"},{"key":"e_1_2_1_20_1","volume-title":"Hayes","author":"Krishnaswamy Smita","year":"2012"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897976"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.28"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0520"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6861093"},{"key":"e_1_2_1_25_1","volume-title":"Retrieved","author":"Inc.","year":"2014"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364500"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917591"},{"key":"e_1_2_1_28_1","volume-title":"Nangate 45nm Open Library","author":"Nangate Inc.","year":"2009"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378282"},{"key":"e_1_2_1_30_1","volume-title":"Retrieved","author":"Nanoscale Integration and Modeling Group","year":"2011"},{"key":"e_1_2_1_31_1","doi-asserted-by":"crossref","volume-title":"Soft Errors in Modern Electronic Systems","author":"Nicolaidis Michael","DOI":"10.1007\/978-1-4419-6993-4"},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2015.65"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479819"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.891036"},{"key":"e_1_2_1_35_1","volume-title":"Soft Error Mechanisms, Modeling and Mitigation","author":"Sayil Selahattin"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024881"},{"key":"e_1_2_1_37_1","volume-title":"2010 11th International Symposium on Quality Electronic Design (ISQED\u201910)","author":"Wang Fan"},{"key":"e_1_2_1_38_1","doi-asserted-by":"crossref","volume-title":"10nm gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation","author":"Wang Luhao","DOI":"10.1109\/S3S.2015.7333552"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2299762"},{"key":"e_1_2_1_40_1","volume-title":"Proceedings of the 7th International Symposium on Quality Electronic Design. IEEE Computer Society, 755--760","author":"Zhang Bin","year":"2006"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2314292"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887832"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3035496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,31]],"date-time":"2022-12-31T07:54:04Z","timestamp":1672473244000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3035496"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5,25]]},"references-count":42,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2017,7,31]]}},"alternative-id":["10.1145\/3035496"],"URL":"https:\/\/doi.org\/10.1145\/3035496","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,5,25]]},"assertion":[{"value":"2016-06-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2017-05-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}