{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T19:50:29Z","timestamp":1730317829254,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":86,"publisher":"ACM","license":[{"start":{"date-parts":[[2017,3,25]],"date-time":"2017-03-25T00:00:00Z","timestamp":1490400000000},"content-version":"vor","delay-in-days":365,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-14-1-0148"],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["N66001-14-1-4040, HR0011-13-2-0005"],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1217553, CCF-1453112, CCF-1438980"],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2016,3,25]]},"DOI":"10.1145\/2872362.2872414","type":"proceedings-article","created":{"date-parts":[[2016,3,28]],"date-time":"2016-03-28T13:24:30Z","timestamp":1459171470000},"page":"217-232","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":99,"title":["OpenPiton"],"prefix":"10.1145","author":[{"given":"Jonathan","family":"Balkind","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Michael","family":"McKeown","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Yaosheng","family":"Fu","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Tri","family":"Nguyen","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Yanqi","family":"Zhou","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Alexey","family":"Lavrov","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Mohammad","family":"Shahrad","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Adi","family":"Fuchs","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Samuel","family":"Payne","sequence":"additional","affiliation":[{"name":"Nvidia, Santa Clara, CA, USA"}]},{"given":"Xiaohua","family":"Liang","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"Matthew","family":"Matl","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]},{"given":"David","family":"Wentzlaff","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}]}],"member":"320","published-online":{"date-parts":[[2016,3,25]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Beri processor 'arcina' release 1. https:\/\/github.com\/CTSRD-CHERI\/beri. Accessed Jan. 2016. Beri processor 'arcina' release 1. https:\/\/github.com\/CTSRD-CHERI\/beri. Accessed Jan. 2016."},{"key":"e_1_3_2_1_2_1","unstructured":"eXtensible Utah Multicore (xum). https:\/\/github.com\/grantae\/mips32r1_xum. Accessed Jan. 2016. eXtensible Utah Multicore (xum). https:\/\/github.com\/grantae\/mips32r1_xum. Accessed Jan. 2016."},{"key":"e_1_3_2_1_3_1","unstructured":"Mips32 release 1. https:\/\/github.com\/grantae\/mips32r1_core. Accessed Jan. 2016. Mips32 release 1. https:\/\/github.com\/grantae\/mips32r1_core. Accessed Jan. 2016."},{"key":"e_1_3_2_1_4_1","unstructured":"Zet processor. http:\/\/zet.aluzina.org\/index.php\/Zet_processor. Accessed Jan. 2016. Zet processor. http:\/\/zet.aluzina.org\/index.php\/Zet_processor. Accessed Jan. 2016."},{"key":"e_1_3_2_1_5_1","unstructured":"Zylin cpu. https:\/\/github.com\/zylin\/zpu. Accessed Jan. 2016. Zylin cpu. https:\/\/github.com\/zylin\/zpu. Accessed Jan. 2016."},{"key":"e_1_3_2_1_6_1","unstructured":"OpenSPARC T1 Microarchitecture Specification. Santa Clara CA 2006. OpenSPARC T1 Microarchitecture Specification. Santa Clara CA 2006."},{"key":"e_1_3_2_1_7_1","unstructured":"OpenSPARC T2 Core Microarchitecture Specification. Santa Clara CA 2007. OpenSPARC T2 Core Microarchitecture Specification. Santa Clara CA 2007."},{"key":"e_1_3_2_1_8_1","unstructured":"\\relax Aeste Works. Aemb multi-threaded 32-bit embedded core family. https:\/\/github.com\/aeste\/aemb. Accessed Jan. 2016. \\relax Aeste Works. Aemb multi-threaded 32-bit embedded core family. https:\/\/github.com\/aeste\/aemb. Accessed Jan. 2016."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2764908"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"R. R. Balwaik S. R. Nayak and A. Jeyakumar. Open-source 32-bit risc soft-core processors. IOSR Journal od VLSI and Signal Processing 2(4):43--46 2013. R. R. Balwaik S. R. Nayak and A. Jeyakumar. Open-source 32-bit risc soft-core processors. IOSR Journal od VLSI and Signal Processing 2(4):43--46 2013.","DOI":"10.9790\/4200-0244346"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629579"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224318"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICISA.2014.6847416"},{"key":"e_1_3_2_1_16_1","first-page":"43","volume-title":"Proceedings of the 8th USENIX Conference on Operating Systems Design and Implementation, OSDI'08","author":"Boyd-Wickizer S.","year":"2008"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/1924943.1924944"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.66"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259028"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_3_2_1_23_1","first-page":"1","volume-title":"IEEE 16th Int. Symposium on","author":"Champagne D.","year":"2010"},{"key":"e_1_3_2_1_24_1","unstructured":"\\relax Cobham Gaisler AB. Grlib ip core user's manual. May 2015. \\relax Cobham Gaisler AB. Grlib ip core user's manual. May 2015."},{"key":"e_1_3_2_1_25_1","first-page":"813","volume-title":"Methods and Tools (DSD), 2010 13th Euromicro Conference on","author":"da Silva A.","year":"2010"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509664"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2013.75"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694353"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830832"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844467"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/233551.233553"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/IGCC.2011.6008574"},{"key":"e_1_3_2_1_34_1","unstructured":"HT-Lab. Cpu86: 8088 fpga ip core. http:\/\/ht-lab.com\/freecores\/cpu8086\/cpu86.html. Accessed Jan. 2016. HT-Lab. Cpu86: 8088 fpga ip core. http:\/\/ht-lab.com\/freecores\/cpu8086\/cpu86.html. Accessed Jan. 2016."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147161"},{"key":"e_1_3_2_1_36_1","unstructured":"T. Instruments. Msp430x1xx family user's guide 2006. T. Instruments. Msp430x1xx family user's guide 2006."},{"key":"e_1_3_2_1_37_1","first-page":"1","volume-title":"Field Programmable Logic and Applications (FPL), 2014 24th International Conference on","author":"Jia R.","year":"2014"},{"key":"e_1_3_2_1_38_1","first-page":"75","volume-title":"IEEE Int. Symposium on","author":"Khalid O.","year":"2013"},{"key":"e_1_3_2_1_39_1","first-page":"1","article-title":"Designing and implementing malicious hardware","volume":"8","author":"King S. T.","year":"2008","journal-title":"LEET"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837369"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942056"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2011.5937096"},{"volume-title":"Prentice Hall Professional","year":"2003","author":"Massa A. J.","key":"e_1_3_2_1_45_1"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.43"},{"volume-title":"The University of Utah","year":"2010","author":"Meakin B. L.","key":"e_1_3_2_1_47_1"},{"key":"e_1_3_2_1_48_1","first-page":"648","volume-title":"Third International Conference on","author":"Mehdizadeh N.","year":"2008"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176877"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"e_1_3_2_1_51_1","unstructured":"S. T. S. Ngiap. Aemb 32-bit microprocessor core datasheet November 2007. S. T. S. Ngiap. Aemb 32-bit microprocessor core datasheet November 2007."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/EDUCON.2010.5492390"},{"key":"e_1_3_2_1_53_1","unstructured":"OpenCores. Altor32 - alternative lightweight openrisc cpu. http:\/\/opencores.org\/project altor32. Accessed Jan. 2016. OpenCores. Altor32 - alternative lightweight openrisc cpu. http:\/\/opencores.org\/project altor32. Accessed Jan. 2016."},{"key":"e_1_3_2_1_54_1","unstructured":"OpenCores. Amber arm-compatible core. http:\/\/opencores.org\/project amber. Accessed Jan. 2016. OpenCores. Amber arm-compatible core. http:\/\/opencores.org\/project amber. Accessed Jan. 2016."},{"key":"e_1_3_2_1_55_1","unstructured":"OpenCores. Openmsp430. http:\/\/opencores.org\/project openmsp430. Accessed Jan. 2016. OpenCores. Openmsp430. http:\/\/opencores.org\/project openmsp430. Accessed Jan. 2016."},{"key":"e_1_3_2_1_56_1","unstructured":"OpenCores. Or1200 openrisc processor. http:\/\/opencores.org\/or1k\/OR1200_OpenRISC_Processor. Accessed Jan. 2016. OpenCores. Or1200 openrisc processor. http:\/\/opencores.org\/or1k\/OR1200_OpenRISC_Processor. Accessed Jan. 2016."},{"key":"e_1_3_2_1_57_1","unstructured":"OpenCores. pAVR. http:\/\/opencores.org\/project pavr. Accessed Jan. 2016. OpenCores. pAVR. http:\/\/opencores.org\/project pavr. Accessed Jan. 2016."},{"key":"e_1_3_2_1_58_1","unstructured":"Oracle. OpenSPARC T1. http:\/\/www.oracle.com\/technetwork\/systems\/opensparc\/opensparc-t1-page-1%444609.html. Oracle. OpenSPARC T1. http:\/\/www.oracle.com\/technetwork\/systems\/opensparc\/opensparc-t1-page-1%444609.html."},{"key":"e_1_3_2_1_59_1","first-page":"1","volume-title":"17th Euro micro conf. on real time systems","author":"Ortego P. M.","year":"2004"},{"volume-title":"Fourth Workshop on Silicon Errors in Logic-System Effects (SELSE). Citeseer","year":"2008","author":"Parulkar I.","key":"e_1_3_2_1_60_1"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176660"},{"volume-title":"Springer Science & Business Media","year":"2012","author":"Polychronopoulos C. D.","key":"e_1_3_2_1_62_1"},{"key":"e_1_3_2_1_63_1","unstructured":"PyHP. PyHP Official Home Page. http:\/\/pyhp.sourceforge.net. PyHP. PyHP Official Home Page. http:\/\/pyhp.sourceforge.net."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254082"},{"key":"e_1_3_2_1_65_1","unstructured":"\\relax Aeroflex Gaisler AB. Sparc v8 32-bit processor leon3\/leon3-ft companioncore data sheet March 2010. \\relax Aeroflex Gaisler AB. Sparc v8 32-bit processor leon3\/leon3-ft companioncore data sheet March 2010."},{"key":"e_1_3_2_1_66_1","unstructured":"\\relax UC Berkeley Architecture Research. The berkeley out-of-order risc-v processor. https:\/\/github.com\/ucb-bar\/riscv-boom. Accessed Jan. 2016. \\relax UC Berkeley Architecture Research. The berkeley out-of-order risc-v processor. https:\/\/github.com\/ucb-bar\/riscv-boom. Accessed Jan. 2016."},{"key":"e_1_3_2_1_67_1","unstructured":"\\relax UC Berkeley Architecture Research. Rocket core. https:\/\/github.com\/ucb-bar\/rocket. Accessed Jan. 2016. \\relax UC Berkeley Architecture Research. Rocket core. https:\/\/github.com\/ucb-bar\/rocket. Accessed Jan. 2016."},{"key":"e_1_3_2_1_68_1","unstructured":"S. RISC. Simply risc s1 core. http:\/\/www.srisc.com\/?s1. Accessed Jan. 2016. S. RISC. Simply risc s1 core. http:\/\/www.srisc.com\/?s1. Accessed Jan. 2016."},{"volume-title":"Xilinx\u00ae Xcell J","year":"2003","author":"Schaumont P.","key":"e_1_3_2_1_69_1"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/1360612.1360617"},{"key":"e_1_3_2_1_71_1","unstructured":"L. Semiconductor. Latticemico32 open free 32-bit soft processor. http:\/\/www.latticesemi.com\/en\/Products\/DesignSoftwareAndIP\/Intellectual%Property\/IPCore\/IPCores02\/LatticeMico32.aspx. Accessed Jan. 2016. L. Semiconductor. Latticemico32 open free 32-bit soft processor. http:\/\/www.latticesemi.com\/en\/Products\/DesignSoftwareAndIP\/Intellectual%Property\/IPCore\/IPCores02\/LatticeMico32.aspx. Accessed Jan. 2016."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665689"},{"key":"e_1_3_2_1_73_1","first-page":"016","article-title":"Soc verification platform based on aemb softcore processor [j]","volume":"4","author":"Shengfeng S.","year":"2010","journal-title":"Microcontrollers & Embedded Systems"},{"volume-title":"Proc. of Workshop on SELSE","year":"2007","author":"Smolens J. C.","key":"e_1_3_2_1_74_1"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516660"},{"volume-title":"ASEE Southeast Section Conference","year":"2007","author":"Strelzoff A.","key":"e_1_3_2_1_76_1"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151022"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2011.5929973"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.5555\/2123870.2123876"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2006.373294"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"issue":"1","key":"e_1_3_2_1_82_1","first-page":"29","article-title":"An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid-State Circuits","volume":"43","author":"Vangal S. R.","year":"2008","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.5555\/1320302.1320834"},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807132"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237040"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"crossref","unstructured":"D. H. Woo and H.-H. S. Lee. Extending amdahl's law for energy-efficient computing in the many-core era. Computer (12):24--31 2008. D. H. Woo and H.-H. S. Lee. Extending amdahl's law for energy-efficient computing in the many-core era. Computer (12):24--31 2008.","DOI":"10.1109\/MC.2008.494"},{"issue":"3","key":"e_1_3_2_1_88_1","first-page":"272","article-title":"Design Test of Computers","volume":"25","author":"Yeh D.","year":"2008","journal-title":"IEEE"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASQED.2010.5548320"}],"event":{"name":"ASPLOS '16: Architectural Support for Programming Languages and Operating Systems","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"],"location":"Atlanta Georgia USA","acronym":"ASPLOS '16"},"container-title":["Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872414","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2872362.2872414","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,4]],"date-time":"2023-09-04T15:05:36Z","timestamp":1693839936000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2872362.2872414"}},"subtitle":["An Open Source Manycore Research Framework"],"short-title":[],"issued":{"date-parts":[[2016,3,25]]},"references-count":86,"alternative-id":["10.1145\/2872362.2872414","10.1145\/2872362"],"URL":"https:\/\/doi.org\/10.1145\/2872362.2872414","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2954679.2872414","asserted-by":"object"},{"id-type":"doi","id":"10.1145\/2980024.2872414","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2016,3,25]]},"assertion":[{"value":"2016-03-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}