{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T07:33:32Z","timestamp":1673422412633},"reference-count":14,"publisher":"Association for Computing Machinery (ACM)","issue":"1","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2013,12]]},"abstract":"Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal\/near-optimal placements on a sufficiently large array size.<\/jats:p>","DOI":"10.1145\/2534394","type":"journal-article","created":{"date-parts":[[2013,12,20]],"date-time":"2013-12-20T19:50:46Z","timestamp":1387569046000},"page":"1-13","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits"],"prefix":"10.1145","volume":"19","author":[{"given":"Chien-Chih","family":"Huang","sequence":"first","affiliation":[{"name":"National Central University, Taoyuan, Taiwan"}]},{"given":"Chin-Long","family":"Wey","sequence":"additional","affiliation":[{"name":"National Chiao Tung University, Hsinchu, Taiwan"}]},{"given":"Jwu-E","family":"Chen","sequence":"additional","affiliation":[{"name":"National Central University, Taoyuan, Taiwan"}]},{"given":"Pei-Wen","family":"Luo","sequence":"additional","affiliation":[{"name":"Industrial Technology Research Institute, Hsinchu, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2013,12,20]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810290"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035587"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices. 131--134","author":"Doh J. S.","year":"2005","unstructured":"Doh , J. S. , Kim , D. W. , Lee , S. H. , Lee , J. B. , Park , Y. K. , Yoo , M. H. , and Kong , J. T . 2005. A unified statistical model for inter-die and intra-die process variation . In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices. 131--134 . DOI: http:\/\/dx.doi.org\/10.1109\/SISPAD. 2005 .201490. 10.1109\/SISPAD.2005.201490 Doh, J. S., Kim, D. W., Lee, S. H., Lee, J. B., Park, Y. K., Yoo, M. H., and Kong, J. T. 2005. A unified statistical model for inter-die and intra-die process variation. In Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices. 131--134. DOI: http:\/\/dx.doi.org\/10.1109\/SISPAD.2005.201490."},{"key":"e_1_2_1_4_1","volume-title":"The Art of Analog Layout","author":"Hastings A.","unstructured":"Hastings , A. 2000. The Art of Analog Layout . Prentice Hall , Upper Saddle River, NJ. Hastings, A. 2000. The Art of Analog Layout. Prentice Hall, Upper Saddle River, NJ."},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the 24th IEEE International SOC Conference. 170--173","author":"Huang C.-C.","year":"2011","unstructured":"Huang , C.-C. , Chen , J.-E. , Luo , P.-W. , and Wey , C. L . 2011. Yield-aware placement optimization for switched-capacitor analog integrated circuits . In Proceedings of the 24th IEEE International SOC Conference. 170--173 . DOI: http:\/\/dx.doi.org\/10.1109\/SOCC. 2011 .6085127. 10.1109\/SOCC.2011.6085127 Huang, C.-C., Chen, J.-E., Luo, P.-W., and Wey, C. L. 2011. Yield-aware placement optimization for switched-capacitor analog integrated circuits. In Proceedings of the 24th IEEE International SOC Conference. 170--173. DOI: http:\/\/dx.doi.org\/10.1109\/SOCC.2011.6085127."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe. 576--580","author":"Khalil D.","unstructured":"Khalil , D. and Dessouky , M . 2002. Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio . In Proceedings of the Conference on Design, Automation and Test in Europe. 576--580 . Khalil, D. and Dessouky, M. 2002. Automatic generation of common-centroid capacitor arrays with arbitrary capacitor ratio. In Proceedings of the Conference on Design, Automation and Test in Europe. 576--580."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.54"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024847"},{"key":"e_1_2_1_10_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference. 772--775","author":"Liu J.","year":"2008","unstructured":"Liu , J. , Dong , S. , Hong , X. , Wang , Y. , He , O. , and Goto , S . 2008. Symmetry constraint based on mismatch analysis for analog layout in SOI technology . In Proceedings of the Asia and South Pacific Design Automation Conference. 772--775 . DOI: http:\/\/dx.doi.org\/10.1109\/ASPDAC. 2008 .4484055. 10.1109\/ASPDAC.2008.4484055 Liu, J., Dong, S., Hong, X., Wang, Y., He, O., and Goto, S. 2008. Symmetry constraint based on mismatch analysis for analog layout in SOI technology. In Proceedings of the Asia and South Pacific Design Automation Conference. 772--775. DOI: http:\/\/dx.doi.org\/10.1109\/ASPDAC.2008.4484055."},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E94.A.352"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006139"},{"key":"e_1_2_1_13_1","volume-title":"Proceedings of the International Conference on Computer-Aided Design. 579--585","author":"Ma Q.","year":"2007","unstructured":"Ma , Q. , Young , E. F. Y. , and Pun , K. P . 2007. Analog placement with common centroid constraints . In Proceedings of the International Conference on Computer-Aided Design. 579--585 . DOI: http:\/\/dx.doi.org\/10.1109\/ICCAD. 2007 .4397327. 10.1109\/ICCAD.2007.4397327 Ma, Q., Young, E. F. Y., and Pun, K. P. 2007. Analog placement with common centroid constraints. In Proceedings of the International Conference on Computer-Aided Design. 579--585. DOI: http:\/\/dx.doi.org\/10.1109\/ICCAD.2007.4397327."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.284714"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884403"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2534394","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,30]],"date-time":"2022-12-30T22:13:12Z","timestamp":1672438392000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2534394"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":14,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,12]]}},"alternative-id":["10.1145\/2534394"],"URL":"https:\/\/doi.org\/10.1145\/2534394","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,12]]},"assertion":[{"value":"2012-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-07-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2013-12-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}