{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T13:47:17Z","timestamp":1725716837236},"publisher-location":"New York, NY, USA","reference-count":48,"publisher":"ACM","funder":[{"DOI":"10.13039\/100000143","name":"Division of Computing and Communication Foundations","doi-asserted-by":"publisher","award":["1147388115247910178820963839CNS 0720645CCF 0811687CCF 0702519"],"id":[{"id":"10.13039\/100000143","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000144","name":"Division of Computer and Network Systems","doi-asserted-by":"publisher","award":["1147388115247910178820963839CNS 0720645CCF 0811687CCF 0702519"],"id":[{"id":"10.13039\/100000144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2011,12,3]]},"DOI":"10.1145\/2155620.2155677","type":"proceedings-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T08:18:26Z","timestamp":1331021906000},"page":"489-500","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["A data layout optimization framework for NUCA-based multicores"],"prefix":"10.1145","author":[{"given":"Yuanrui","family":"Zhang","sequence":"first","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Wei","family":"Ding","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Mahmut","family":"Kandemir","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Jun","family":"Liu","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]},{"given":"Ohyoung","family":"Jang","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA"}]}],"member":"320","published-online":{"date-parts":[[2011,12,3]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Polylib - a library of polyhedral functions. http:\/\/icps.u-strasbg.fr\/polylib\/. Polylib - a library of polyhedral functions. http:\/\/icps.u-strasbg.fr\/polylib\/."},{"key":"e_1_3_2_1_2_1","unstructured":"Singlechip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm. Singlechip cloud computer. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1826.htm."},{"key":"e_1_3_2_1_3_1","unstructured":"Teraflops research chip. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1449.htm. Teraflops research chip. http:\/\/techresearch.intel.com\/articles\/Tera-Scale\/1449.htm."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/209936.209954"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016765"},{"key":"e_1_3_2_1_7_1","volume-title":"SPEComp: A new benchmark suite for measuring parallel computer performance","author":"Aslot V.","year":"2001","unstructured":"V. Aslot SPEComp: A new benchmark suite for measuring parallel computer performance . 2001 . V. Aslot et al. SPEComp: A new benchmark suite for measuring parallel computer performance. 2001."},{"key":"e_1_3_2_1_8_1","volume-title":"LCPC","author":"Bastoul C.","year":"2003","unstructured":"C. Bastoul Putting polyhedral loop transformations to work . LCPC , 2003 . C. Bastoul et al. Putting polyhedral loop transformations to work. LCPC, 2003."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1788374.1788386"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536401"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/645671.665529"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305231"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391628"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/62297.62322"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956577"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956577"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.31"},{"key":"e_1_3_2_1_19_1","volume-title":"ICCD","author":"Chou C.","year":"2008","unstructured":"C. Chou and R. Marculescu . Contention-aware application mapping for network-on-chip communication architectures . ICCD , 2008 . C. Chou and R. Marculescu. Contention-aware application mapping for network-on-chip communication architectures. ICCD, 2008."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403616"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301670"},{"key":"e_1_3_2_1_23_1","volume-title":"Splitting data objects to increase cache utilization","author":"Franz M.","year":"1998","unstructured":"M. Franz and T. Kistler . Splitting data objects to increase cache utilization . 1998 . M. Franz and T. Kistler. Splitting data objects to increase cache utilization. 1998."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/224170.224500"},{"key":"e_1_3_2_1_25_1","volume-title":"IMPACT","author":"Grosser T.","year":"2011","unstructured":"T. Grosser Polyhedral optimization in LLVM . IMPACT , 2011 . T. Grosser et al. Polly - Polyhedral optimization in LLVM. IMPACT, 2011."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/165939.165959"},{"key":"e_1_3_2_1_27_1","volume-title":"ISCA","author":"Hardavellas N.","year":"2009","unstructured":"N. Hardavellas : Data placement in distributed shared caches . ISCA , 2009 . N. Hardavellas et al. R-NUCA: Data placement in distributed shared caches. ISCA, 2009."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555779"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.752779"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/645676.663643"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.5555\/2190025.2190066"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/224170.224495"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/369028.369051"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.2"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.5555\/977395.977673"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.18"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.36"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/233561.233564"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263655"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2005.1596983"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277661"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/HIPC.2009.5433220"},{"key":"e_1_3_2_1_49_1","volume-title":"CGO","author":"So B.","year":"2004","unstructured":"B. So Custom data layout for memory parallelism . CGO , 2004 . B. So et al. Custom data layout for memory parallelism. CGO, 2004."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113449"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.5555\/1509456.1509585"}],"event":{"name":"MICRO-44: The 44th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["IEEE","ACM Association for Computing Machinery","UFRGS Universidade Federal do Rio Grande do Sul","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE-CS Computer Society"],"location":"Porto Alegre Brazil","acronym":"MICRO-44"},"container-title":["Proceedings of the 44th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2155620.2155677","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T12:36:06Z","timestamp":1673440566000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2155620.2155677"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,3]]},"references-count":48,"alternative-id":["10.1145\/2155620.2155677","10.1145\/2155620"],"URL":"https:\/\/doi.org\/10.1145\/2155620.2155677","relation":{},"subject":[],"published":{"date-parts":[[2011,12,3]]},"assertion":[{"value":"2011-12-03","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}