{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T18:28:35Z","timestamp":1725733715479},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","funder":[{"DOI":"10.13039\/501100001665","name":"Agence Nationale de la Recherche","doi-asserted-by":"publisher","award":["ANR-07-ARFU-010"],"id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2010,10,24]]},"DOI":"10.1145\/1873548.1873554","type":"proceedings-article","created":{"date-parts":[[2010,11,1]],"date-time":"2010-11-01T13:32:23Z","timestamp":1288618343000},"page":"1-8","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":25,"title":["Countering early evaluation"],"prefix":"10.1145","author":[{"given":"Shivam","family":"Bhasin","sequence":"first","affiliation":[{"name":"Institut TELECOM \/ TELECOM ParisTech, Paris Cedex, France"}]},{"given":"Sylvain","family":"Guilley","sequence":"additional","affiliation":[{"name":"Institut TELECOM \/ TELECOM ParisTech, Paris Cedex, France"}]},{"given":"Florent","family":"Flament","sequence":"additional","affiliation":[{"name":"Institut TELECOM \/ TELECOM ParisTech, Paris Cedex, France"}]},{"given":"Nidhal","family":"Selmane","sequence":"additional","affiliation":[{"name":"Institut TELECOM \/ TELECOM ParisTech, Paris Cedex, France"}]},{"given":"Jean-Luc","family":"Danger","sequence":"additional","affiliation":[{"name":"Institut TELECOM \/ TELECOM ParisTech, Paris Cedex, France"}]}],"member":"320","published-online":{"date-parts":[[2010,10,24]]},"reference":[{"key":"e_1_3_2_1_1_1","series-title":"LNCS","first-page":"309","volume-title":"Proceedings of CHES'01","author":"Akkar M.-L.","year":"2001","unstructured":"M.-L. Akkar and C. Giraud . An Implementation of DES and AES Secure against Some Attacks . In LNCS, editor, Proceedings of CHES'01 , volume 2162 of LNCS , pages 309 -- 318 . Springer , May 2001 . Paris, France. M.-L. Akkar and C. Giraud. An Implementation of DES and AES Secure against Some Attacks. In LNCS, editor, Proceedings of CHES'01, volume 2162 of LNCS, pages 309--318. Springer, May 2001. Paris, France."},{"key":"e_1_3_2_1_2_1","first-page":"213","volume-title":"ReConFig","author":"Bhasin S.","year":"2009","unstructured":"S. Bhasin , J.-L. Danger , F. Flament , T. Graba , S. Guilley , Y. Mathieu , M. Nassar , L. Sauvage , and N. Selmane . Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow . In ReConFig , pages 213 -- 218 . IEEE Computer Society , December 9--11 2009 . Canc\u00fan, Quintana Roo, M\u00e9xico, DOI: 10.1109\/ReConFig.2009.50, http:\/\/hal.archives-ouvertes.fr\/hal-00411843\/en\/. 10.1109\/ReConFig.2009.50 10.1109\/ReConFig.2009.50 S. Bhasin, J.-L. Danger, F. Flament, T. Graba, S. Guilley, Y. Mathieu, M. Nassar, L. Sauvage, and N. Selmane. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. In ReConFig, pages 213--218. IEEE Computer Society, December 9--11 2009. Canc\u00fan, Quintana Roo, M\u00e9xico, DOI: 10.1109\/ReConFig.2009.50, http:\/\/hal.archives-ouvertes.fr\/hal-00411843\/en\/. 10.1109\/ReConFig.2009.50"},{"key":"e_1_3_2_1_3_1","series-title":"LNCS","first-page":"513","volume-title":"CRYPTO","author":"Biham E.","year":"1997","unstructured":"E. Biham and A. Shamir . Differential Fault Analysis of Secret Key Cryptosystems . In CRYPTO , volume 1294 of LNCS , pages 513 -- 525 . Springer , August 1997 . Santa Barbara, California, USA. DOI: 10.1007\/BFb0052259. 10.1007\/BFb0052259 E. Biham and A. Shamir. Differential Fault Analysis of Secret Key Cryptosystems. In CRYPTO, volume 1294 of LNCS, pages 513--525. Springer, August 1997. Santa Barbara, California, USA. DOI: 10.1007\/BFb0052259."},{"key":"e_1_3_2_1_4_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1007\/978-3-540-85053-3_27","volume-title":"CHES, 10th International Workshop","author":"Gierlichs B.","year":"2008","unstructured":"B. Gierlichs , L. Batina , P. Tuyls , and B. Preneel . Mutual information analysis . In CHES, 10th International Workshop , volume 5154 of Lecture Notes in Computer Science , pages 426 -- 442 . Springer , August 10--13 2008 . Washington, D.C., USA. 10.1007\/978-3-540-85053-3_27 B. Gierlichs, L. Batina, P. Tuyls, and B. Preneel. Mutual information analysis. In CHES, 10th International Workshop, volume 5154 of Lecture Notes in Computer Science, pages 426--442. Springer, August 10--13 2008. Washington, D.C., USA. 10.1007\/978-3-540-85053-3_27"},{"key":"e_1_3_2_1_5_1","series-title":"Lecture Notes in Computer Science","first-page":"198","volume-title":"CHES","author":"Golic J. D.","year":"2002","unstructured":"J. D. Golic and C. Tymen . Multiplicative Masking and Power Analysis of AES . In CHES , volume 2523 of Lecture Notes in Computer Science , pages 198 -- 212 . Springer , August 13--15 2002 . San Francisco, USA. J. D. Golic and C. Tymen. Multiplicative Masking and Power Analysis of AES. In CHES, volume 2523 of Lecture Notes in Computer Science, pages 198--212. Springer, August 13--15 2002. San Francisco, USA."},{"key":"e_1_3_2_1_6_1","first-page":"29","volume-title":"HOST","author":"Guilley S.","year":"2008","unstructured":"S. Guilley , S. Chaudhuri , L. Sauvage , T. Graba , J.-L. Danger , P. Hoogvorst , V.-N. Vong , and M. Nassar . Place-and-Route Impact on the Security of DPL Designs in FPGAs . In HOST , pages 29 -- 35 . IEEE Computer Society , 2008 . June 9, Anaheim, USA. ISBN = 978-1-4244-2401-6. 10.1109\/HST.2008.4559042 S. Guilley, S. Chaudhuri, L. Sauvage, T. Graba, J.-L. Danger, P. Hoogvorst, V.-N. Vong, and M. Nassar. Place-and-Route Impact on the Security of DPL Designs in FPGAs. In HOST, pages 29--35. IEEE Computer Society, 2008. June 9, Anaheim, USA. ISBN = 978-1-4244-2401-6. 10.1109\/HST.2008.4559042"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.109"},{"key":"e_1_3_2_1_8_1","first-page":"5D","author":"Guilley S.","year":"2008","unstructured":"S. Guilley , F. Flament , Y. Mathieu , and R. Pacalet . Security Evaluation of a Balanced Quasi-Delay Insensitive Library. In DCIS, Grenoble, France, nov 2008 . IEEE. Session 5D -- Reliable and Secure Architectures, ISBN: 978-2-84813-124-5. S. Guilley, F. Flament, Y. Mathieu, and R. Pacalet. Security Evaluation of a Balanced Quasi-Delay Insensitive Library. In DCIS, Grenoble, France, nov 2008. IEEE. Session 5D -- Reliable and Secure Architectures, ISBN: 978-2-84813-124-5.","journal-title":"Security Evaluation of a Balanced Quasi-Delay Insensitive Library. In DCIS, Grenoble, France, nov"},{"key":"e_1_3_2_1_9_1","series-title":"LNCS","first-page":"383","volume-title":"CHES","author":"Guilley S.","year":"2005","unstructured":"S. Guilley , P. Hoogvorst , Y. Mathieu , and R. Pacalet . The \"Backend Duplication\" Method . In CHES , volume 3659 of LNCS , pages 383 -- 397 . Springer , 2005 . August 29th -- September 1st, Edinburgh, Scotland, UK. 10.1007\/11545262_28 S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet. The \"Backend Duplication\" Method. In CHES, volume 3659 of LNCS, pages 383--397. Springer, 2005. August 29th -- September 1st, Edinburgh, Scotland, UK. 10.1007\/11545262_28"},{"key":"e_1_3_2_1_10_1","first-page":"16","volume-title":"SSIRI","author":"Guilley S.","year":"2008","unstructured":"S. Guilley , L. Sauvage , J.-L. Danger , T. Graba , and Y. Mathieu . Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs . In SSIRI , pages 16 -- 23 , Yokohama, Japan, jul 2008 . IEEE Computer Society. DOI: 10.1109\/SSIRI.2008.31, http:\/\/hal.archives-ouvertes.fr\/hal-00259153\/en\/. 10.1109\/SSIRI.2008.31 10.1109\/SSIRI.2008.31 S. Guilley, L. Sauvage, J.-L. Danger, T. Graba, and Y. Mathieu. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. In SSIRI, pages 16--23, Yokohama, Japan, jul 2008. IEEE Computer Society. DOI: 10.1109\/SSIRI.2008.31, http:\/\/hal.archives-ouvertes.fr\/hal-00259153\/en\/. 10.1109\/SSIRI.2008.31"},{"key":"e_1_3_2_1_11_1","series-title":"LNCS","first-page":"388","volume-title":"Proceedings of CRYPTO'99","author":"Kocher P. C.","year":"1999","unstructured":"P. C. Kocher , J. Jaffe , and B. Jun . Differential Power Analysis . In Proceedings of CRYPTO'99 , volume 1666 of LNCS , pages 388 -- 397 . Springer-Verlag , 1999 . P. C. Kocher, J. Jaffe, and B. Jun. Differential Power Analysis. In Proceedings of CRYPTO'99, volume 1666 of LNCS, pages 388--397. Springer-Verlag, 1999."},{"key":"e_1_3_2_1_12_1","first-page":"131","volume-title":"IOLTS","author":"Kulikowski K. J.","year":"2006","unstructured":"K. J. Kulikowski , M. G. Karpovsky , and A. Taubin . Power Attacks on Secure Hardware Based on Early Propagation of Data . In IOLTS , pages 131 -- 138 . IEEE Computer Society , 2006 . Como, Italy. 10.1109\/IOLTS.2006.49 K. J. Kulikowski, M. G. Karpovsky, and A. Taubin. Power Attacks on Secure Hardware Based on Early Propagation of Data. In IOLTS, pages 131--138. IEEE Computer Society, 2006. Como, Italy. 10.1109\/IOLTS.2006.49"},{"key":"e_1_3_2_1_13_1","series-title":"LNCS","first-page":"157","volume-title":"Proceedings of CHES'05","author":"Mangard S.","year":"2005","unstructured":"S. Mangard , N. Pramstaller , and E. Oswald . Successfully Attacking Masked AES Hardware Implementations . In LNCS, editor, Proceedings of CHES'05 , volume 3659 of LNCS , pages 157 -- 171 . Springer , August 29 -- September 1 2005 . Edinburgh, Scotland, UK. 10.1007\/11545262_12 S. Mangard, N. Pramstaller, and E. Oswald. Successfully Attacking Masked AES Hardware Implementations. In LNCS, editor, Proceedings of CHES'05, volume 3659 of LNCS, pages 157--171. Springer, August 29 -- September 1 2005. Edinburgh, Scotland, UK. 10.1007\/11545262_12"},{"key":"e_1_3_2_1_14_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1007\/978-3-540-76788-6_21","volume-title":"ICISC","author":"Moradi A.","year":"2007","unstructured":"A. Moradi , M. Salmasizadeh , and M. T. M. Shalmani . Power analysis attacks on mdpl and drsl implementations . In ICISC , volume 4817 of Lecture Notes in Computer Science , pages 259 -- 272 . Springer , November 29--30 2007 . A. Moradi, M. Salmasizadeh, and M. T. M. Shalmani. Power analysis attacks on mdpl and drsl implementations. In ICISC, volume 4817 of Lecture Notes in Computer Science, pages 259--272. Springer, November 29--30 2007."},{"key":"e_1_3_2_1_15_1","volume-title":"Practical DPA Attacks on MDPL. In First International Workshop on Information Forensics and Security (WIFS). IEEE Signal Processing Society, December 6--9 2009","author":"Mulder E. D.","year":"2009","unstructured":"E. D. Mulder , B. Gierlichs , B. Preneel , and I. Verbauwhede . Practical DPA Attacks on MDPL. In First International Workshop on Information Forensics and Security (WIFS). IEEE Signal Processing Society, December 6--9 2009 . London, United Kingdom. Also http:\/\/eprint.iacr.org\/ 2009 \/231. E. D. Mulder, B. Gierlichs, B. Preneel, and I. Verbauwhede. Practical DPA Attacks on MDPL. In First International Workshop on Information Forensics and Security (WIFS). IEEE Signal Processing Society, December 6--9 2009. London, United Kingdom. Also http:\/\/eprint.iacr.org\/2009\/231."},{"key":"e_1_3_2_1_17_1","series-title":"LNCS","first-page":"77","volume-title":"CHES","author":"Piret G.","year":"2003","unstructured":"G. Piret and J.-J. Quisquater . A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad . In CHES , volume 2779 of LNCS , pages 77 -- 88 . Springer , September 2003 . Cologne, Germany. G. Piret and J.-J. Quisquater. A Differential Fault Attack Technique against SPN Structures, with Application to the AES and Khazad. In CHES, volume 2779 of LNCS, pages 77--88. Springer, September 2003. Cologne, Germany."},{"key":"e_1_3_2_1_18_1","series-title":"LNCS","first-page":"172","volume-title":"Proceedings of CHES'05","author":"Popp T.","year":"2005","unstructured":"T. Popp and S. Mangard . Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints . In Proceedings of CHES'05 , volume 3659 of LNCS , pages 172 -- 186 . Springer , August 29 -- September 1 2005 . Edinburgh, Scotland, UK. 10.1007\/11545262_13 T. Popp and S. Mangard. Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. In Proceedings of CHES'05, volume 3659 of LNCS, pages 172--186. Springer, August 29 -- September 1 2005. Edinburgh, Scotland, UK. 10.1007\/11545262_13"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e91-a.1.176"},{"key":"e_1_3_2_1_20_1","first-page":"640","volume-title":"DATE","author":"Sauvage L.","year":"2009","unstructured":"L. Sauvage , S. Guilley , J.-L. Danger , Y. Mathieu , and M. Nassar . Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints . In DATE , pages 640 -- 645 , Nice, France , apr 2009 . IEEE Computer Society . L. Sauvage, S. Guilley, J.-L. Danger, Y. Mathieu, and M. Nassar. Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints. In DATE, pages 640--645, Nice, France, apr 2009. IEEE Computer Society."},{"key":"e_1_3_2_1_21_1","first-page":"73","volume-title":"FDTC","author":"Selmane N.","year":"2009","unstructured":"N. Selmane , S. Bhasin , S. Guilley , T. Graba , and J.-L. Danger . WDDL is Protected Against Setup Time Violation Attacks . In FDTC , pages 73 -- 83 . IEEE Computer Society, September 6th 2009 . In conjunction with CHES'09, Lausanne, Switzerland. DOI: 10.1109\/FDTC.2009.40; Online version: http:\/\/hal.archives-ouvertes.fr\/hal-00410135\/en\/. 10.1109\/FDTC.2009.40 10.1109\/FDTC.2009.40; N. Selmane, S. Bhasin, S. Guilley, T. Graba, and J.-L. Danger. WDDL is Protected Against Setup Time Violation Attacks. In FDTC, pages 73--83. IEEE Computer Society, September 6th 2009. In conjunction with CHES'09, Lausanne, Switzerland. DOI: 10.1109\/FDTC.2009.40; Online version: http:\/\/hal.archives-ouvertes.fr\/hal-00410135\/en\/. 10.1109\/FDTC.2009.40"},{"key":"e_1_3_2_1_22_1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"443","DOI":"10.1007\/978-3-642-01001-9_26","volume-title":"EUROCRYPT","author":"Standaert F.-X.","year":"2009","unstructured":"F.-X. Standaert , T. Malkin , and M. Yung . A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks . In EUROCRYPT , volume 5479 of Lecture Notes in Computer Science , pages 443 -- 461 . Springer , April 26--30 2009 . Cologne, Germany. 10.1007\/978-3-642-01001-9_26 F.-X. Standaert, T. Malkin, and M. Yung. A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks. In EUROCRYPT, volume 5479 of Lecture Notes in Computer Science, pages 443--461. Springer, April 26--30 2009. Cologne, Germany. 10.1007\/978-3-642-01001-9_26"},{"key":"e_1_3_2_1_23_1","series-title":"LNCS","first-page":"255","volume-title":"CHES","author":"Suzuki D.","year":"2006","unstructured":"D. Suzuki and M. Saeki . Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style . In CHES , volume 4249 of LNCS , pages 255 -- 269 . Springer , 2006 . Yokohama, Japan. http:\/\/dx.doi.org\/10.1007\/11894063_21. 10.1007\/11894063_21 10.1007\/11894063_21 D. Suzuki and M. Saeki. Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style. In CHES, volume 4249 of LNCS, pages 255--269. Springer, 2006. Yokohama, Japan. http:\/\/dx.doi.org\/10.1007\/11894063_21. 10.1007\/11894063_21"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e91-a.1.184"},{"key":"e_1_3_2_1_25_1","series-title":"LNCS","first-page":"354","volume-title":"Proceedings of CHES'05","author":"Tiri K.","year":"2005","unstructured":"K. Tiri , D. Hwang , A. Hodjat , B.-C. Lai , S. Yang , P. Schaumont , and I. Verbauwhede . Prototype IC with WDDL and Differential Routing -- DPA Resistance Assessment . In LNCS, editor, Proceedings of CHES'05 , volume 3659 of LNCS , pages 354 -- 365 . Springer , August 29 -- September 1 2005 . Edinburgh, Scotland, UK. 10.1007\/11545262_26 K. Tiri, D. Hwang, A. Hodjat, B.-C. Lai, S. Yang, P. Schaumont, and I. Verbauwhede. Prototype IC with WDDL and Differential Routing -- DPA Resistance Assessment. In LNCS, editor, Proceedings of CHES'05, volume 3659 of LNCS, pages 354--365. Springer, August 29 -- September 1 2005. Edinburgh, Scotland, UK. 10.1007\/11545262_26"},{"key":"e_1_3_2_1_26_1","first-page":"246","volume-title":"DATE'04","author":"Tiri K.","year":"2004","unstructured":"K. Tiri and I. Verbauwhede . A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation . In DATE'04 , pages 246 -- 251 . IEEE Computer Society , February 2004 . Paris, France. DOI: 10.1109\/DATE.2004.1268856. 10.1109\/DATE.2004.1268856 K. Tiri and I. Verbauwhede. A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In DATE'04, pages 246--251. IEEE Computer Society, February 2004. Paris, France. DOI: 10.1109\/DATE.2004.1268856."},{"key":"e_1_3_2_1_27_1","first-page":"143","volume-title":"Proceedings of WCC \/ CARDIS","author":"Tiri K.","year":"2004","unstructured":"K. Tiri and I. Verbauwhede . Place and Route for Secure Standard Cell Design. In Kluwer, editor , Proceedings of WCC \/ CARDIS , pages 143 -- 158 , Aug 2004 . Toulouse, France. K. Tiri and I. Verbauwhede. Place and Route for Secure Standard Cell Design. In Kluwer, editor, Proceedings of WCC \/ CARDIS, pages 143--158, Aug 2004. Toulouse, France."},{"key":"e_1_3_2_1_28_1","unstructured":"N.\n Veyrat-Charvillon\n and \n F.-X.\n Standaert\n .\n Mutual Information Analysis: How When and Why? In CHES volume \n 5747\n of \n LNCS pages \n 429\n --\n 443\n . \n Springer September 6--9 \n 2009\n . Lausanne Switzerland. 10.1007\/978-3-642-04138-9_30 N. Veyrat-Charvillon and F.-X. Standaert. Mutual Information Analysis: How When and Why? In CHES volume 5747 of LNCS pages 429--443. Springer September 6--9 2009. Lausanne Switzerland. 10.1007\/978-3-642-04138-9_30"}],"event":{"name":"ESWeek '10: Sixth Embedded Systems Week","sponsor":["CEDA Council on Electronic Design Automation","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","IEEE CS"],"location":"Scottsdale Arizona","acronym":"ESWeek '10"},"container-title":["Proceedings of the 5th Workshop on Embedded Systems Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1873548.1873554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,9]],"date-time":"2023-01-09T07:49:47Z","timestamp":1673250587000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1873548.1873554"}},"subtitle":["an approach towards robust dual-rail precharge logic"],"short-title":[],"issued":{"date-parts":[[2010,10,24]]},"references-count":27,"alternative-id":["10.1145\/1873548.1873554","10.1145\/1873548"],"URL":"https:\/\/doi.org\/10.1145\/1873548.1873554","relation":{},"subject":[],"published":{"date-parts":[[2010,10,24]]},"assertion":[{"value":"2010-10-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}