{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,5,11]],"date-time":"2024-05-11T05:19:07Z","timestamp":1715404747804},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIGARCH Comput. Archit. News"],"published-print":{"date-parts":[[1986,5]]},"abstract":"In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access latency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. Write buffers are often included in a pipelined machine to avoid processor waiting on writes. In a shared memory multiprocessor, there are more advantages in buffering memory requests, since each memory access has to traverse the memory- processor interconnection and has to compete with memory requests issued by different processors. Buffering, however, can cause logical problems in multiprocessors. These problems are aggravated if each processor has a private memory in which shared writable data may be present, such as in a cache-based system or in a system with a distributed global memory. In this paper, we analyze the benefits and problems associated with the buffering of memory requests in shared memory multiprocessors. We show that the logical problem of buffering is directly related to the problem of synchronization. A simple model is presented to evaluate the performance improvement resulting from buffering.<\/jats:p>","DOI":"10.1145\/17356.17406","type":"journal-article","created":{"date-parts":[[2004,7,22]],"date-time":"2004-07-22T06:26:10Z","timestamp":1090477570000},"page":"434-442","source":"Crossref","is-referenced-by-count":158,"title":["Memory access buffering in multiprocessors"],"prefix":"10.1145","volume":"14","author":[{"given":"M.","family":"Dubois","sequence":"first","affiliation":[{"name":"Computer Research Institute, University of Southern California, Los Angeles, California"}]},{"given":"C.","family":"Scheurich","sequence":"additional","affiliation":[{"name":"Computer Research Institute, University of Southern California, Los Angeles, California"}]},{"given":"F.","family":"Briggs","sequence":"additional","affiliation":[{"name":"Dept. of Electrical and Computer Eng., Rice University, Houston, Texas"}]}],"member":"320","published-online":{"date-parts":[[1986,5]]},"reference":[{"key":"e_1_2_1_1_2","doi-asserted-by":"publisher","DOI":"10.1145\/356901.356903"},{"key":"e_1_2_1_2_2","volume-title":"June","author":"Special","year":"1985","unstructured":"Special session on commercial cache-based multiprocessors , in the Proceedings of the 12th International Symposium on Computer Architecture , June 1985 . Special session on commercial cache-based multiprocessors, in the Proceedings of the 12th International Symposium on Computer Architecture, June 1985."},{"key":"e_1_2_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/800188.805450"},{"key":"e_1_2_1_4_2","author":"Briggs F.A.","year":"1983","unstructured":"F.A. Briggs and M. Dubois , \"Effectiveness of Private Caches in Multiprocessors with Parallel-Pipelined Memories,\" IEEE Transaction8 on Computers , January 1983 . F.A. Briggs and M. Dubois, \"Effectiveness of Private Caches in Multiprocessors with Parallel-Pipelined Memories,\" IEEE Transaction8 on Computers, January 1983.","journal-title":"\"Effectiveness of Private Caches in Multiprocessors with Parallel-Pipelined Memories,\" IEEE Transaction8 on Computers"},{"key":"e_1_2_1_5_2","first-page":"27","author":"Censier L. M.","year":"1978","unstructured":"L. M. Censier and P. Feautrier , \"A New Solution to Coherence Problems in Multieache Systems,\" IEEE Transactions on Computers , Vol. C - 27 , No.12, December 1978 . L. M. Censier and P. Feautrier,\"A New Solution to Coherence Problems in Multieache Systems,\" IEEE Transactions on Computers, Vol. C-27, No.12, December 1978.","journal-title":"\"A New Solution to Coherence Problems in Multieache Systems,\" IEEE Transactions on Computers"},{"key":"e_1_2_1_6_2","volume-title":"June","author":"Chin C-Y","year":"1984","unstructured":"C-Y Chin and K. Hwang ,\" Paeket-switehing Networks for Multiprocessor and Data-flow Computers,\" Proceedings of the 11th International Symposium on Computer Architecture , June 1984 . C-Y Chin and K. Hwang,\"Paeket-switehing Networks for Multiprocessor and Data-flow Computers,\" Proceedings of the 11th International Symposium on Computer Architecture, June 1984."},{"key":"e_1_2_1_7_2","unstructured":"W. W. Collier \"Architectures for Systems of Parallel Processes \" IBM Technical Report TR00.3253 January 27 1984. W. W. Collier \"Architectures for Systems of Parallel Processes \" IBM Technical Report TR00.3253 January 27 1984."},{"key":"e_1_2_1_8_2","unstructured":"W. W. Collier \"Reasoning about Parallel Architectures \" submitted to JACM 1985. W. W. Collier \"Reasoning about Parallel Architectures \" submitted to JACM 1985."},{"key":"e_1_2_1_9_2","first-page":"31","author":"Dubois M.","year":"1982","unstructured":"M. Dubois and F.A. Briggs , \"Effects of Caehe Coherency in Multiproeessors,\" IEEE Transactions on Computers , Vol. C - 31 , No. 11, November 1982 . M. Dubois and F.A. Briggs, \"Effects of Caehe Coherency in Multiproeessors,\" IEEE Transactions on Computers, Vol. C-31, No. 11, November 1982.","journal-title":"\"Effects of Caehe Coherency in Multiproeessors,\" IEEE Transactions on Computers"},{"key":"e_1_2_1_10_2","volume-title":"October","author":"Gehringer E.F.","year":"1982","unstructured":"E.F. Gehringer , , \" The Cm* Testbed,\" IEEE Computer , October 1982 . E.F. Gehringer, et al., \"The Cm* Testbed,\" IEEE Computer, October 1982."},{"key":"e_1_2_1_11_2","unstructured":"K. Hwang and F.A. Briggs Computer Architecture and Parallel Processing Mac Craw-Hill. K. Hwang and F.A. Briggs Computer Architecture and Parallel Processing Mac Craw-Hill."},{"key":"e_1_2_1_12_2","volume-title":"Kai Hwang Ed.","author":"Supercomputero Tutorial","year":"1984","unstructured":"Tutorial on Supercomputero : Design and Applications , Kai Hwang Ed. , IEEE Computer Society , 1984 . Tutorial on Supercomputero: Design and Applications, Kai Hwang Ed., IEEE Computer Society, 1984."},{"key":"e_1_2_1_13_2","unstructured":"P. M. Kogge \"The Architecture of Pipelined Computers \" Mac Grow-Hill 1981. P. M. Kogge \"The Architecture of Pipelined Computers \" Mac Grow-Hill 1981."},{"key":"e_1_2_1_14_2","unstructured":"D. Kroft \"Lookup-free Instruction Fetch\/Prefetch Cache Organization \" Proceedings of the 8th Annual Syrups- Mum on Computer Architecture June 1981. D. Kroft \"Lookup-free Instruction Fetch\/Prefetch Cache Organization \" Proceedings of the 8th Annual Syrups- Mum on Computer Architecture June 1981."},{"key":"e_1_2_1_15_2","volume-title":"New Directions and Recent Results","author":"Kung H.T.","year":"1976","unstructured":"H.T. Kung , \" Synchronized and Asynchronous Parallel Algorithms for multiprocessors,\" in Algorithms and Complexity : New Directions and Recent Results , J.F. Traub Ed., New York : Academic Press , 1976 . H.T. Kung, \"Synchronized and Asynchronous Parallel Algorithms for multiprocessors,\" in Algorithms and Complexity: New Directions and Recent Results, J.F. Traub Ed., New York: Academic Press, 1976."},{"key":"e_1_2_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/359545.359563"},{"key":"e_1_2_1_17_2","first-page":"28","author":"Lamport L.","year":"1979","unstructured":"L. Lamport , \" How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs ,\" IEEE Transaction8 on Computers , Vol. C - 28 , No. 9, September 1979 . L. Lamport, \"How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,\" IEEE Transaction8 on Computers, Vol. C-28, No. 9, September 1979.","journal-title":"Computers"},{"key":"e_1_2_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/800046.801671"},{"key":"e_1_2_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/356887.356892"}],"container-title":["ACM SIGARCH Computer Architecture News"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/17356.17406","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,6]],"date-time":"2022-12-06T05:57:56Z","timestamp":1670306276000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/17356.17406"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,5]]},"references-count":19,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1986,5]]}},"alternative-id":["10.1145\/17356.17406"],"URL":"https:\/\/doi.org\/10.1145\/17356.17406","relation":{},"ISSN":["0163-5964"],"issn-type":[{"value":"0163-5964","type":"print"}],"subject":[],"published":{"date-parts":[[1986,5]]}}}