{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T18:49:17Z","timestamp":1730314157056,"version":"3.28.0"},"publisher-location":"New York, NY, USA","reference-count":42,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2007,9,30]]},"DOI":"10.1145\/1289881.1289923","type":"proceedings-article","created":{"date-parts":[[2007,10,14]],"date-time":"2007-10-14T08:51:38Z","timestamp":1192351898000},"page":"238-247","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["INTACTE"],"prefix":"10.1145","author":[{"given":"Rahul","family":"Nagpal","sequence":"first","affiliation":[{"name":"Indian Institute of Science"}]},{"given":"Arvind","family":"Madan","sequence":"additional","affiliation":[{"name":"Indian Institute of Science"}]},{"given":"Amrutur","family":"Bhardwaj","sequence":"additional","affiliation":[{"name":"Indian Institute of Science"}]},{"given":"Y. N.","family":"Srikant","sequence":"additional","affiliation":[{"name":"Indian Institute of Science"}]}],"member":"320","published-online":{"date-parts":[[2007,9,30]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM MPCore. http:\/\/www.arm.com. ARM MPCore. http:\/\/www.arm.com."},{"key":"e_1_3_2_1_2_1","unstructured":"BSIM4.6.0. http:\/\/www- device.eecs.berkeley.edu\/ bsim3\/bsim4.html. BSIM4.6.0. http:\/\/www- device.eecs.berkeley.edu\/ bsim3\/bsim4.html."},{"key":"e_1_3_2_1_3_1","unstructured":"HSPICE. http:\/\/www.synopsys.com\/products\/hspice.html. HSPICE. http:\/\/www.synopsys.com\/products\/hspice.html."},{"key":"e_1_3_2_1_4_1","unstructured":"Intel Multi-Core. http:\/\/www.intel.com\/multi-core\/index.htm. Intel Multi-Core. http:\/\/www.intel.com\/multi-core\/index.htm."},{"key":"e_1_3_2_1_5_1","unstructured":"International Technology Roadmap for Semiconductors. http:\/\/www.itrs.net\/. International Technology Roadmap for Semiconductors. http:\/\/www.itrs.net\/."},{"key":"e_1_3_2_1_6_1","unstructured":"MATLAB. http:\/\/www.mathworks.com\/products\/matlab\/. MATLAB. http:\/\/www.mathworks.com\/products\/matlab\/."},{"key":"e_1_3_2_1_7_1","unstructured":"OMAP. focus.ti.com\/omap\/docs\/omaphomepage.tsp. OMAP. focus.ti.com\/omap\/docs\/omaphomepage.tsp."},{"key":"e_1_3_2_1_8_1","unstructured":"Predictive Technology Model. http:\/\/www.eas.asu.edu\/~ptm\/. Predictive Technology Model. http:\/\/www.eas.asu.edu\/~ptm\/."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/998680.1006734"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2007.15"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.21"},{"key":"e_1_3_2_1_12_1","first-page":"2007","article-title":"A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs. In Proc. of","author":"Banerjee K.","year":"2001","unstructured":"K. Banerjee and A. Mehrotra . A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs. In Proc. of IEEE Transactions on Electron Devices, pages 2001 { 2007 , November 2002. K. Banerjee and A. Mehrotra. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs. In Proc. of IEEE Transactions on Electron Devices, pages 2001{2007, November 2002.","journal-title":"IEEE Transactions on Electron Devices, pages"},{"issue":"111","key":"e_1_3_2_1_13_1","first-page":"2","article-title":"first look","volume":"2003","author":"Baxter M.","year":"2003","unstructured":"M. Baxter . Amd64 opteron : first look . Linux J. , 2003 ( 111 ): 2 , 2003 . M. Baxter. Amd64 opteron: first look. Linux J., 2003(111):2, 2003.","journal-title":"Linux J."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2003.1202354"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.5555\/774861.774896"},{"key":"e_1_3_2_1_17_1","volume-title":"Hewlett-Packard","author":"Faraboschi P.","year":"1998","unstructured":"P. Faraboschi , G. Brown , J. A. Fisher , and G. Desoli . Clustered Instruction-level Parallel Processors. Technical report , Hewlett-Packard , 1998 . P. Faraboschi, G. Brown, J. A. Fisher, and G. Desoli. Clustered Instruction-level Parallel Processors. Technical report, Hewlett-Packard, 1998."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339682"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266815"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.820055"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009944"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781137"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876436"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/762488.762494"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612245"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.820651"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.5555\/1018426.1020407"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/977091.977155"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1007\/11945918_48"},{"key":"e_1_3_2_1_34_1","first-page":"348","volume-title":"Proc. of Euromicro Conf.","author":"Pechanek G. G.","year":"2000","unstructured":"G. G. Pechanek and S. Vassiliadis . The ManArray Embedded Processor Architecture . In Proc. of Euromicro Conf. , pages 348 -- 355 , 2000 . G. G. Pechanek and S. Vassiliadis. The ManArray Embedded Processor Architecture. In Proc. of Euromicro Conf., pages 348--355, 2000."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.5555\/1148882.1148884"},{"key":"e_1_3_2_1_36_1","unstructured":"Texas Instruments Inc. TMS320C6000 CPU and Instruction Set reference Guide. http:\/\/www.ti.com\/sc\/docs\/products\/dsp\/c6000\/index.htm 1998. Texas Instruments Inc. TMS320C6000 CPU and Instruction Set reference Guide. http:\/\/www.ti.com\/sc\/docs\/products\/dsp\/c6000\/index.htm 1998."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.443.0379"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.5555\/827245.827319"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379022"},{"key":"e_1_3_2_1_40_1","first-page":"105","volume-title":"Proc. of Symp. on Microarchitecture","author":"Wang H.","year":"2003","unstructured":"H. Wang , L.-S. Peh , and S. Malik . Power-driven Design of Router Microarchitectures in On-chip Networks . In Proc. of Symp. on Microarchitecture , page 105 , 2003 . H. Wang, L.-S. Peh, and S. Malik. Power-driven Design of Router Microarchitectures in On-chip Networks. In Proc. of Symp. on Microarchitecture, page 105, 2003."},{"key":"e_1_3_2_1_41_1","first-page":"294","volume-title":"Proc. of the intl. symp. on Microarchitecture","author":"Wang H.-S.","year":"2002","unstructured":"H.-S. Wang , X. Zhu , L.-S. Peh , and S. Malik . Orion: a power-performance simulator for interconnection networks . In Proc. of the intl. symp. on Microarchitecture , pages 294 -- 305 , 2002 . H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: a power-performance simulator for interconnection networks. In Proc. of the intl. symp. on Microarchitecture, pages 294--305, 2002."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.461.0027"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.509850"}],"event":{"name":"ESWEEK07: Third Embedded Systems Week","sponsor":["ACM Association for Computing Machinery","SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Salzburg Austria","acronym":"ESWEEK07"},"container-title":["Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1289881.1289923","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,9]],"date-time":"2023-01-09T18:29:41Z","timestamp":1673288981000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1289881.1289923"}},"subtitle":["an interconnect area, delay, and energy estimation tool for microarchitectural explorations"],"short-title":[],"issued":{"date-parts":[[2007,9,30]]},"references-count":42,"alternative-id":["10.1145\/1289881.1289923","10.1145\/1289881"],"URL":"https:\/\/doi.org\/10.1145\/1289881.1289923","relation":{},"subject":[],"published":{"date-parts":[[2007,9,30]]},"assertion":[{"value":"2007-09-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}