{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T01:29:11Z","timestamp":1725672551222},"publisher-location":"New York, NY, USA","reference-count":24,"publisher":"ACM","content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2006,6,28]]},"DOI":"10.1145\/1183401.1183427","type":"proceedings-article","created":{"date-parts":[[2007,1,17]],"date-time":"2007-01-17T01:15:56Z","timestamp":1168996556000},"page":"167-176","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["A scalable low power issue queue for large instruction window processors"],"prefix":"10.1145","author":[{"given":"Rajesh","family":"Vivekanandham","sequence":"first","affiliation":[{"name":"Indian Institute of Science, Bangalore, India"}]},{"given":"Bharadwaj","family":"Amrutur","sequence":"additional","affiliation":[{"name":"Indian Institute of Science, Bangalore, India"}]},{"given":"R.","family":"Govindarajan","sequence":"additional","affiliation":[{"name":"Indian Institute of Science, Bangalore, India"}]}],"member":"320","published-online":{"date-parts":[[2006,6,28]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339691"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956554"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564026"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566454"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1044823.1044825"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859647"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545221"},{"key":"e_1_3_2_1_9_1","author":"Gonzalez R.","year":"1996","unstructured":"R. Gonzalez and M. Horowitz . Energy dissipation in general purpose microprocessors. In IEEE Journal of Solid-State Circuits , 1996 . R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. In IEEE Journal of Solid-State Circuits, 1996.","journal-title":"Energy dissipation in general purpose microprocessors. In IEEE Journal of Solid-State Circuits"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564028"},{"key":"e_1_3_2_1_11_1","volume-title":"Proceedings of 29th International Symposium on Computer Architecture","author":"Hrishikesh M.","year":"2002","unstructured":"M. Hrishikesh , N. P. Jouppi , K. I. Farkas , D. Burger , and S. W. K. P. Shivakumar . The optimal useful logic depth per pipeline stages is 6-8 fo4 . In Proceedings of 29th International Symposium on Computer Architecture , 2002 . M. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, and S. W. K. P. Shivakumar. The optimal useful logic depth per pipeline stages is 6-8 fo4. In Proceedings of 29th International Symposium on Computer Architecture, 2002."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10014"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566456"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196116"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859623"},{"key":"e_1_3_2_1_16_1","volume-title":"Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research. In Workshop on Workload Characterization in International Conference on Computer Design","author":"KleinOsowski A.","year":"2000","unstructured":"A. KleinOsowski , J. Flynn , N. Meares , and D. J. Lilja . Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research. In Workshop on Workload Characterization in International Conference on Computer Design , 2000 . A. KleinOsowski, J. Flynn, N. Meares, and D. J. Lilja. Adapting the SPEC2000 benchmarks suite for simulation-based computer architecture research. In Workshop on Workload Characterization in International Conference on Computer Design, 2000."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/580550.876427"},{"key":"e_1_3_2_1_18_1","unstructured":"Mosis.org. www.mosis.org\/cgi-bin\/cgiwrap\/umosis\/swp\/params\/ibm-013\/t4bj-params.txt. Mosis.org. www.mosis.org\/cgi-bin\/cgiwrap\/umosis\/swp\/params\/ibm-013\/t4bj-params.txt."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264201"},{"key":"e_1_3_2_1_20_1","volume-title":"Workshop on Complexity-Effective Design held in conjunction with the 28th Annual International Symposium on Computer Architecture","author":"Sato T.","year":"2004","unstructured":"T. Sato , Y. Nakamura , and I. Arita . Revisiting direct tag search algorithm on superscalar processors . In Workshop on Complexity-Effective Design held in conjunction with the 28th Annual International Symposium on Computer Architecture , 2004 . T. Sato, Y. Nakamura, and I. Arita. Revisiting direct tag search algorithm on superscalar processors. In Workshop on Complexity-Effective Design held in conjunction with the 28th Annual International Symposium on Computer Architecture, 2004."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_22_1","volume-title":"Western Research Laboratory","author":"Shivakumar P.","year":"2001","unstructured":"P. Shivakumar and N. P. Jouppi . Cacti 3.0: An integrated cache timing, power, and area model. Technical report , Western Research Laboratory , Compaq Computer Corporation , 2001 . P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Technical report, Western Research Laboratory, Compaq Computer Corporation, 2001."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360136"},{"key":"e_1_3_2_1_25_1","volume-title":"Western Research Laboratory","author":"Wall D.","year":"1993","unstructured":"D. Wall . Limits of instruction-level parallelism. Technical report , Western Research Laboratory , Compaq Computer Corporation , 1993 . D. Wall. Limits of instruction-level parallelism. Technical report, Western Research Laboratory, Compaq Computer Corporation, 1993."},{"key":"e_1_3_2_1_26_1","volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","author":"Weste N.","year":"2005","unstructured":"N. Weste and D. Harris . CMOS VLSI Design: A Circuits and Systems Perspective , 3 rd edition. Addison-Wesley Publishing Company , 2005 . N. Weste and D. Harris. CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition. Addison-Wesley Publishing Company, 2005.","edition":"3"}],"event":{"name":"ICS06: International Conference on Supercomputing 2006","sponsor":["ACM Association for Computing Machinery","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Cairns Queensland Australia","acronym":"ICS06"},"container-title":["Proceedings of the 20th annual international conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/1183401.1183427","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,11]],"date-time":"2023-01-11T07:10:30Z","timestamp":1673421030000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/1183401.1183427"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,6,28]]},"references-count":24,"alternative-id":["10.1145\/1183401.1183427","10.1145\/1183401"],"URL":"https:\/\/doi.org\/10.1145\/1183401.1183427","relation":{},"subject":[],"published":{"date-parts":[[2006,6,28]]},"assertion":[{"value":"2006-06-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}