{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T23:54:55Z","timestamp":1648770895025},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[1995,6]]},"abstract":" A common technique to improve the reliability of loop (or ring) networks is by introducing link redundancy; that is, by providing several alternative paths for communication between pairs of nodes. With alternate paths between nodes, the network can now sustain several node and link failures by bypassing the faulty components. However, faults occurring at strategic locations in a ring can prevent the computation by disrupting I\/O operations, blocking the flow of information, or even segmenting the structure into pieces which can no longer be suitable for any practical purpose. <\/jats:p> An extensive characterization of fault-tolerance in ring topologies is given in this paper. This characterization augments the results known in the literature to date. The characterization has revealed several properties which describe the problem of constructing subrings and linear arrays in the presence of node failures in the original ring for a specified link configuration. Also in this paper, bounds are established on the degree of fault tolerance achievable in a redundant loop network, with a given degree of redundancy, when performing a computation that requires a minimal number of operational nodes. Also the bounds on the size of the problems guaranteed to be solved in the presence of a given number of faults in the network are derived. <\/jats:p>","DOI":"10.1142\/s0218126695000151","type":"journal-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T11:59:25Z","timestamp":1100260765000},"page":"199-213","source":"Crossref","is-referenced-by-count":2,"title":["ON RELIABILITY ANALYSIS OF CHORDAL RINGS"],"prefix":"10.1142","volume":"05","author":[{"given":"AMIYA","family":"NAYAK","sequence":"first","affiliation":[{"name":"Center for Parallel & Distributed Computing, School of Computer Science, Carleton University, Ottawa, Canada, K1S 5B6, Canada"}]},{"given":"NICOLA","family":"SANTORO","sequence":"additional","affiliation":[{"name":"Center for Parallel & Distributed Computing, School of Computer Science, Carleton University, Ottawa, Canada, K1S 5B6, Canada"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126695000151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T17:12:23Z","timestamp":1565197943000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126695000151"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,6]]},"references-count":0,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1995,6]]}},"alternative-id":["10.1142\/S0218126695000151"],"URL":"https:\/\/doi.org\/10.1142\/s0218126695000151","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,6]]}}}